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Drivers/CMSIS/Core/Include/cmsis_armcc.h

+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

Drivers/CMSIS/Core/Include/cmsis_armclang.h

+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

Drivers/CMSIS/Core/Include/cmsis_compiler.h

+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

Drivers/CMSIS/Core/Include/cmsis_gcc.h

+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

Drivers/CMSIS/Core/Include/cmsis_iccarm.h

+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

Drivers/CMSIS/Core/Include/cmsis_version.h

+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

Drivers/CMSIS/Core/Include/core_armv8mbl.h

+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Drivers/CMSIS/Core/Include/core_cm0.h

+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Drivers/CMSIS/Core/Include/core_cm0plus.h

+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Drivers/CMSIS/Core/Include/core_cm1.h

+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Drivers/CMSIS/Core/Include/core_sc000.h

+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Drivers/CMSIS/Core/Include/mpu_armv7.h

+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

Drivers/CMSIS/Core/Include/mpu_armv8.h

+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

Drivers/CMSIS/Core/Include/tz_context.h

+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c

+/******************************************************************************
+ * @file     main_s.c
+ * @brief    Code template for secure main function
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Use CMSE intrinsics */
+#include <arm_cmse.h>
+ 
+#include "RTE_Components.h"
+#include CMSIS_device_header
+ 
+/* TZ_START_NS: Start address of non-secure application */
+#ifndef TZ_START_NS
+#define TZ_START_NS (0x200000U)
+#endif
+ 
+/* typedef for non-secure callback functions */
+typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
+ 
+/* Secure main() */
+int main(void) {
+  funcptr_void NonSecure_ResetHandler;
+ 
+  /* Add user setup code for secure part here*/
+ 
+  /* Set non-secure main stack (MSP_NS) */
+  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+ 
+  /* Get non-secure reset handler */
+  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
+ 
+  /* Start non-secure state software application */
+  NonSecure_ResetHandler();
+ 
+  /* Non-secure software does not return, this code is not executed */
+  while (1) {
+    __NOP();
+  }
+}

Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c

+/******************************************************************************
+ * @file     tz_context.c
+ * @brief    Context Management for Armv8-M TrustZone - Sample implementation
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "tz_context.h"
+
+/// Number of process slots (threads may call secure library code)
+#ifndef TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SLOTS     8U
+#endif
+
+/// Stack size of the secure library code
+#ifndef TZ_PROCESS_STACK_SIZE
+#define TZ_PROCESS_STACK_SIZE      256U
+#endif
+
+typedef struct {
+  uint32_t sp_top;      // stack space top
+  uint32_t sp_limit;    // stack space limit
+  uint32_t sp;          // current stack pointer
+} stack_info_t;
+
+static stack_info_t ProcessStackInfo  [TZ_PROCESS_STACK_SLOTS];
+static uint64_t     ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
+static uint32_t     ProcessStackFreeSlot = 0xFFFFFFFFU;
+
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_InitContextSystem_S (void) {
+  uint32_t n;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
+    ProcessStackInfo[n].sp = 0U;
+    ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
+    ProcessStackInfo[n].sp_top   = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
+    *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
+  }
+  *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
+
+  ProcessStackFreeSlot = 0U;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  // Privileged Thread Mode using PSP
+  __set_CONTROL(0x02U);
+
+  return 1U;    // Success
+}
+
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+__attribute__((cmse_nonsecure_entry))
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
+  uint32_t slot;
+
+  (void)module; // Ignore (fixed Stack size)
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
+    return 0U;  // No slot available
+  }
+
+  slot = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
+
+  ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
+
+  return (slot + 1U);
+}
+
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+  ProcessStackInfo[slot].sp = 0U;
+
+  *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = slot;
+
+  return 1U;    // Success
+}
+
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  // Setup process stack pointer and stack limit
+  __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
+  __set_PSP   (ProcessStackInfo[slot].sp);
+
+  return 1U;    // Success
+}
+
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+  uint32_t sp;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  sp = __get_PSP();
+  if ((sp < ProcessStackInfo[slot].sp_limit) ||
+      (sp > ProcessStackInfo[slot].sp_top)) {
+    return 0U;  // SP out of range
+  }
+  ProcessStackInfo[slot].sp = sp;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  return 1U;    // Success
+}

Drivers/CMSIS/Core_A/Include/cmsis_armcc.h

+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A  == 1))
+  #define __ARM_ARCH_7A__           1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __forceinline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                     __breakpoint(value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR (Floating Point Status/Control)
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+/**
+  \brief   Set FPSCR (Floating Point Status/Control)
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+/** \brief  Get CPSR (Current Program Status Register)
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+
+/** \brief  Set CPSR (Current Program Status Register)
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  __regCPSR = cpsr;
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void)
+{
+  return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
+{
+  MOV  r1, lr
+  MSR  CPSR_C, r0
+  BX   r1
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP(void)
+{
+  MOV  r0, sp
+  BX   lr
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
+{
+  MOV  sp, r0
+  BX   lr
+}
+
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYSStack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
+{
+  ARM
+  PRESERVE8
+
+  MRS     R1, CPSR
+  CPS     #0x1F       ;no effect in USR mode
+  MOV     R0, SP
+  MSR     CPSR_c, R1  ;no effect in USR mode
+  ISB
+  BX      LR
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
+{
+  ARM
+  PRESERVE8
+
+  MRS     R1, CPSR
+  CPS     #0x1F       ;no effect in USR mode
+  MOV     SP, R0
+  MSR     CPSR_c, R1  ;no effect in USR mode
+  ISB
+  BX      LR
+}
+
+/** \brief  Get FPEXC (Floating Point Exception Control Register)
+    \return               Floating Point Exception Control Register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC (Floating Point Exception Control Register)
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
+#define __get_CP64(cp, op1, Rt, CRm) \
+  do { \
+    uint32_t ltmp, htmp; \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+    (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
+  } while(0)
+
+#define __set_CP64(cp, op1, Rt, CRm) \
+  do { \
+    const uint64_t tmp = (Rt); \
+    const uint32_t ltmp = (uint32_t)(tmp); \
+    const uint32_t htmp = (uint32_t)(tmp >> 32U); \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+  } while(0)
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE __ASM void __FPU_Enable(void)
+{
+        ARM
+
+        //Permit access to VFP/NEON, registers by modifying CPACR
+        MRC     p15,0,R1,c1,c0,2
+        ORR     R1,R1,#0x00F00000
+        MCR     p15,0,R1,c1,c0,2
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+        ISB
+
+        //Enable VFP/NEON
+        VMRS    R1,FPEXC
+        ORR     R1,R1,#0x40000000
+        VMSR    FPEXC,R1
+
+        //Initialise VFP/NEON registers to 0
+        MOV     R2,#0
+
+        //Initialise D16 registers to 0
+        VMOV    D0, R2,R2
+        VMOV    D1, R2,R2
+        VMOV    D2, R2,R2
+        VMOV    D3, R2,R2
+        VMOV    D4, R2,R2
+        VMOV    D5, R2,R2
+        VMOV    D6, R2,R2
+        VMOV    D7, R2,R2
+        VMOV    D8, R2,R2
+        VMOV    D9, R2,R2
+        VMOV    D10,R2,R2
+        VMOV    D11,R2,R2
+        VMOV    D12,R2,R2
+        VMOV    D13,R2,R2
+        VMOV    D14,R2,R2
+        VMOV    D15,R2,R2
+
+  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+        //Initialise D32 registers to 0
+        VMOV    D16,R2,R2
+        VMOV    D17,R2,R2
+        VMOV    D18,R2,R2
+        VMOV    D19,R2,R2
+        VMOV    D20,R2,R2
+        VMOV    D21,R2,R2
+        VMOV    D22,R2,R2
+        VMOV    D23,R2,R2
+        VMOV    D24,R2,R2
+        VMOV    D25,R2,R2
+        VMOV    D26,R2,R2
+        VMOV    D27,R2,R2
+        VMOV    D28,R2,R2
+        VMOV    D29,R2,R2
+        VMOV    D30,R2,R2
+        VMOV    D31,R2,R2
+  ENDIF
+
+        //Initialise FPSCR to a known state
+        VMRS    R2,FPSCR
+        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+        AND     R2,R2,R3
+        VMSR    FPSCR,R2
+
+        BX      LR
+}
+
+#endif /* __CMSIS_ARMCC_H */

Drivers/CMSIS/Core_A/Include/cmsis_armclang.h

+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __attribute__((always_inline))
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __builtin_arm_wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __builtin_arm_wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __builtin_arm_sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)   __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT          __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ           (uint8_t)__builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#define __get_FPSCR      __builtin_arm_get_fpscr
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#define __set_FPSCR      __builtin_arm_set_fpscr
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+	return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP()
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr()
+{
+  uint32_t cpsr;
+  uint32_t result;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     %1, sp     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+   );
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, %1     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+   );
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if __ARM_NEON == 1
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#endif /* __CMSIS_ARMCLANG_H */

Drivers/CMSIS/Core_A/Include/cmsis_compiler.h

+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include "cmsis_iccarm.h"
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #define CMSIS_DEPRECATED          __attribute__((deprecated))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __attribute__((aligned(x)))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __attribute__((packed))
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #define CMSIS_DEPRECATED          __attribute__((deprecated))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __packed__
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                     _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
+    #define CMSIS_DEPRECATED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __weak
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  @packed
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

Drivers/CMSIS/Core_A/Include/cmsis_cp15.h

+/**************************************************************************//**
+ * @file     cmsis_cp15.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.1
+ * @date     07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_CP15_H
+#define __CMSIS_CP15_H
+
+/** \brief  Get ACTLR
+    \return               Auxiliary Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return(result);
+}
+
+/** \brief  Set ACTLR
+    \param [in]    actlr  Auxiliary Control value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
+{
+  __set_CP(15, 0, actlr, 1, 0, 1);
+}
+
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 2);
+  return result;
+}
+
+/** \brief  Set CPACR
+    \param [in]    cpacr  Coprocessor Access Control value to set
+ */
+__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
+{
+  __set_CP(15, 0, cpacr, 1, 0, 2);
+}
+
+/** \brief  Get DFSR
+    \return               Data Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 0);
+  return result;
+}
+
+/** \brief  Set DFSR
+    \param [in]    dfsr  Data Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
+{
+  __set_CP(15, 0, dfsr, 5, 0, 0);
+}
+
+/** \brief  Get IFSR
+    \return               Instruction Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 1);
+  return result;
+}
+
+/** \brief  Set IFSR
+    \param [in]    ifsr  Instruction Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
+{
+  __set_CP(15, 0, ifsr, 5, 0, 1);
+}
+
+/** \brief  Get ISR
+    \return               Interrupt Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ISR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 1, 0);
+  return result;
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 4, result, 15, 0, 0);
+  return result;
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 2, 0, 0);
+  return result;
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
+{
+  __set_CP(15, 0, ttbr0, 2, 0, 0);
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 3, 0, 0);
+  return result;
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
+{
+  __set_CP(15, 0, dacr, 3, 0, 0);
+}
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
+{
+  __set_CP(15, 0, sctlr, 1, 0, 0);
+}
+
+/** \brief  Get SCTLR
+    \return               System Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 0);
+  return result;
+}
+
+/** \brief  Set ACTRL
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
+{
+  __set_CP(15, 0, actrl, 1, 0, 1);
+}
+
+/** \brief  Get ACTRL
+    \return               Auxiliary Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return result;
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 0, 0, 5);
+  return result;
+}
+
+/** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 0);
+  return result;
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
+{
+  __set_CP(15, 0, vbar, 12, 0, 0);
+}
+
+/** \brief  Get MVBAR
+
+    This function returns the value of the Monitor Vector Base Address Register.
+
+    \return               Monitor Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 1);
+  return result;
+}
+
+/** \brief  Set MVBAR
+
+    This function assigns the given value to the Monitor Vector Base Address Register.
+
+    \param [in]    mvbar  Monitor Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
+{
+  __set_CP(15, 0, mvbar, 12, 0, 1);
+}
+
+#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
+    defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+    defined(DOXYGEN)
+
+/** \brief  Set CNTFRQ
+
+  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+  \param [in]    value  CNTFRQ Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 0, 0);
+}
+
+/** \brief  Get CNTFRQ
+
+    This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+    \return               CNTFRQ Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 0 , 0);
+  return result;
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 0);
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 0);
+  return result;
+}
+
+/** \brief  Get CNTPCT
+
+    This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
+
+    \return               CNTPCT Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
+{
+  uint64_t result;
+  __get_CP64(15, 0, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CVAL
+
+  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+  \param [in]    value  CNTP_CVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
+{
+  __set_CP64(15, 2, value, 14);
+}
+
+/** \brief  Get CNTP_CVAL
+
+    This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+    \return               CNTP_CVAL Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
+{
+  uint64_t result;
+  __get_CP64(15, 2, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 1);
+}
+
+/** \brief  Get CNTP_CTL register
+    \return               CNTP_CTL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 1);
+  return result;
+}
+
+#endif
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 8, 7, 0);
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 6);
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 0);
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 10, 1);
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 6, 1);
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 14, 1);
+}
+
+/** \brief  Set CSSELR
+ */
+__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
+  __set_CP(15, 2, value, 0, 0, 0);
+}
+
+/** \brief  Get CSSELR
+    \return CSSELR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
+  __get_CP(15, 2, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Set CCSIDR
+    \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
+ */
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
+{
+  __set_CSSELR(value);
+}
+
+/** \brief  Get CCSIDR
+    \return CCSIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
+  __get_CP(15, 1, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Get CLIDR
+    \return CLIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
+  __get_CP(15, 1, result, 0, 0, 1);
+  return result;
+}
+
+/** \brief  Set DCISW
+ */
+__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 6, 2);
+}
+
+/** \brief  Set DCCSW
+ */
+__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 10, 2);
+}
+
+/** \brief  Set DCCISW
+ */
+__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 14, 2);
+}
+
+#endif

Drivers/CMSIS/Core_A/Include/cmsis_gcc.h

+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __attribute__((always_inline))
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   CMSIS_DEPRECATED
+ #define  CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+/**
+  \brief   Send Event
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE  uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U) {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             (uint8_t)__builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE  void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE  void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return Floating Point Status/Control register value
+*/
+__STATIC_FORCEINLINE  uint32_t __get_FPSCR(void)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_get_fpscr) 
+  // Re-enable using built-in when GCC has been fixed
+  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    return __builtin_arm_get_fpscr();
+  #else
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+  #endif
+  #else
+    return(0U);
+  #endif
+}
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in] fpscr  Floating Point Status/Control value to set
+*/
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_set_fpscr)
+  // Re-enable using built-in when GCC has been fixed
+  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    __builtin_arm_set_fpscr(fpscr);
+  #else
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+  #endif
+  #else
+    (void)fpscr;
+  #endif
+}
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+    return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr = __get_CPSR();
+  uint32_t result;
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     %0, sp   " : "=r"(result) : : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr = __get_CPSR();
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     sp, %0   " : : "r" (topOfProcStack) : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h

+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.6
+ * @date     02. March 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#pragma language=extended
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_7A__
+/* Macro already defined */
+#else
+  #if defined(__ARM7A__)
+    #define __ARM_ARCH_7A__ 1
+  #endif
+#endif
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED      __attribute__((deprecated))
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+  {
+    return *(__packed uint16_t*)(ptr);
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+  {
+    *(__packed uint16_t*)(ptr) = val;;
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+  {
+    return *(__packed uint32_t*)(ptr);
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+  {
+    *(__packed uint32_t*)(ptr) = val;;
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#if 0
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+  #pragma language=save
+  #pragma language=extended
+  __packed struct  __iar_u32 { uint32_t v; };
+  #pragma language=restore
+  #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq    __iar_builtin_enable_fiq
+  #define __disable_fault_irq   __iar_builtin_disable_fiq
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+  #if __FPU_PRESENT
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+  #else
+    #define __get_FPSCR()             ( 0 )
+  #endif
+
+  #define __set_FPSCR(VALUE)          (__arm_wsr("FPSCR", VALUE))
+
+  #define __get_CPSR()                (__arm_rsr("CPSR"))
+  #define __get_mode()                (__get_CPSR() & 0x1FU)
+
+  #define __set_CPSR(VALUE)           (__arm_wsr("CPSR", (VALUE)))
+  #define __set_mode(VALUE)           (__arm_wsr("CPSR_c", (VALUE)))
+
+
+  #define __get_FPEXC()       (__arm_rsr("FPEXC"))
+  #define __set_FPEXC(VALUE)    (__arm_wsr("FPEXC", VALUE))
+
+  #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
+    ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
+
+  #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
+    (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
+
+  #define __get_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+
+  #define __set_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+  #include "cmsis_cp15.h"
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #define __SSAT    __iar_builtin_SSAT
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #define __USAT    __iar_builtin_USAT
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #define __SADD8   __iar_builtin_SADD8
+  #define __QADD8   __iar_builtin_QADD8
+  #define __SHADD8  __iar_builtin_SHADD8
+  #define __UADD8   __iar_builtin_UADD8
+  #define __UQADD8  __iar_builtin_UQADD8
+  #define __UHADD8  __iar_builtin_UHADD8
+  #define __SSUB8   __iar_builtin_SSUB8
+  #define __QSUB8   __iar_builtin_QSUB8
+  #define __SHSUB8  __iar_builtin_SHSUB8
+  #define __USUB8   __iar_builtin_USUB8
+  #define __UQSUB8  __iar_builtin_UQSUB8
+  #define __UHSUB8  __iar_builtin_UHSUB8
+  #define __SADD16  __iar_builtin_SADD16
+  #define __QADD16  __iar_builtin_QADD16
+  #define __SHADD16 __iar_builtin_SHADD16
+  #define __UADD16  __iar_builtin_UADD16
+  #define __UQADD16 __iar_builtin_UQADD16
+  #define __UHADD16 __iar_builtin_UHADD16
+  #define __SSUB16  __iar_builtin_SSUB16
+  #define __QSUB16  __iar_builtin_QSUB16
+  #define __SHSUB16 __iar_builtin_SHSUB16
+  #define __USUB16  __iar_builtin_USUB16
+  #define __UQSUB16 __iar_builtin_UQSUB16
+  #define __UHSUB16 __iar_builtin_UHSUB16
+  #define __SASX    __iar_builtin_SASX
+  #define __QASX    __iar_builtin_QASX
+  #define __SHASX   __iar_builtin_SHASX
+  #define __UASX    __iar_builtin_UASX
+  #define __UQASX   __iar_builtin_UQASX
+  #define __UHASX   __iar_builtin_UHASX
+  #define __SSAX    __iar_builtin_SSAX
+  #define __QSAX    __iar_builtin_QSAX
+  #define __SHSAX   __iar_builtin_SHSAX
+  #define __USAX    __iar_builtin_USAX
+  #define __UQSAX   __iar_builtin_UQSAX
+  #define __UHSAX   __iar_builtin_UHSAX
+  #define __USAD8   __iar_builtin_USAD8
+  #define __USADA8  __iar_builtin_USADA8
+  #define __SSAT16  __iar_builtin_SSAT16
+  #define __USAT16  __iar_builtin_USAT16
+  #define __UXTB16  __iar_builtin_UXTB16
+  #define __UXTAB16 __iar_builtin_UXTAB16
+  #define __SXTB16  __iar_builtin_SXTB16
+  #define __SXTAB16 __iar_builtin_SXTAB16
+  #define __SMUAD   __iar_builtin_SMUAD
+  #define __SMUADX  __iar_builtin_SMUADX
+  #define __SMMLA   __iar_builtin_SMMLA
+  #define __SMLAD   __iar_builtin_SMLAD
+  #define __SMLADX  __iar_builtin_SMLADX
+  #define __SMLALD  __iar_builtin_SMLALD
+  #define __SMLALDX __iar_builtin_SMLALDX
+  #define __SMUSD   __iar_builtin_SMUSD
+  #define __SMUSDX  __iar_builtin_SMUSDX
+  #define __SMLSD   __iar_builtin_SMLSD
+  #define __SMLSDX  __iar_builtin_SMLSDX
+  #define __SMLSLD  __iar_builtin_SMLSLD
+  #define __SMLSLDX __iar_builtin_SMLSLDX
+  #define __SEL     __iar_builtin_SEL
+  #define __QADD    __iar_builtin_QADD
+  #define __QSUB    __iar_builtin_QSUB
+  #define __PKHBT   __iar_builtin_PKHBT
+  #define __PKHTB   __iar_builtin_PKHTB
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if !__FPU_PRESENT
+  #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if !__FPU_PRESENT
+  #define __get_FPSCR() (0)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq        __enable_interrupt
+  #define __disable_irq       __disable_interrupt
+  #define __enable_fault_irq    __enable_fiq
+  #define __disable_fault_irq   __disable_fiq
+  #define __NOP               __no_operation
+
+  #define __get_xPSR          __get_PSR
+
+  __IAR_FT void __set_mode(uint32_t mode)
+  {
+    __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+  }
+
+  __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+  {
+    return __LDREX((unsigned long *)ptr);
+  }
+
+  __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+  {
+    return __STREX(value, (unsigned long *)ptr);
+  }
+
+
+  __IAR_FT uint32_t __RRX(uint32_t value)
+  {
+    uint32_t result;
+    __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+    return(result);
+  }
+
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  __IAR_FT uint32_t __get_FPEXC(void)
+  {
+  #if (__FPU_PRESENT == 1)
+    uint32_t result;
+    __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+    return(result);
+  #else
+    return(0);
+  #endif
+  }
+
+  __IAR_FT void __set_FPEXC(uint32_t fpexc)
+  {
+  #if (__FPU_PRESENT == 1)
+    __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+  #endif
+  }
+
+
+  #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
+    __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+  #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
+    __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+  #define __get_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+  #define __set_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+  #include "cmsis_cp15.h"
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+
+__IAR_FT uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr;
+  uint32_t result;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     %1, sp     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+   );
+  return result;
+}
+
+__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, %1     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+   );
+}
+
+#define __get_mode()                (__get_CPSR() & 0x1FU)
+
+__STATIC_INLINE
+void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#ifdef __ARM_ADVANCED_SIMD__
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        MOV32   R3,#0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2          \n");
+}
+
+
+
+#undef __IAR_FT
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

Drivers/CMSIS/Core_A/Include/irq_ctrl.h

+/**************************************************************************//**
+ * @file     irq_ctrl.h
+ * @brief    Interrupt Controller API header file
+ * @version  V1.0.0
+ * @date     23. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef IRQ_CTRL_H_
+#define IRQ_CTRL_H_
+
+#include <stdint.h>
+
+#ifndef IRQHANDLER_T
+#define IRQHANDLER_T
+/// Interrupt handler data type
+typedef void (*IRQHandler_t) (void);
+#endif
+
+#ifndef IRQN_ID_T
+#define IRQN_ID_T
+/// Interrupt ID number data type
+typedef int32_t IRQn_ID_t;
+#endif
+
+/* Interrupt mode bit-masks */
+#define IRQ_MODE_TRIG_Pos           (0U)
+#define IRQ_MODE_TRIG_Msk           (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+#define IRQ_MODE_TRIG_LEVEL         (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_LOW     (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_HIGH    (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
+#define IRQ_MODE_TRIG_EDGE          (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_FALLING  (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_BOTH     (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
+
+#define IRQ_MODE_TYPE_Pos           (3U)
+#define IRQ_MODE_TYPE_Msk           (0x01UL << IRQ_MODE_TYPE_Pos)
+#define IRQ_MODE_TYPE_IRQ           (0x00UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU IRQ line
+#define IRQ_MODE_TYPE_FIQ           (0x01UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU FIQ line
+
+#define IRQ_MODE_DOMAIN_Pos         (4U)
+#define IRQ_MODE_DOMAIN_Msk         (0x01UL << IRQ_MODE_DOMAIN_Pos)
+#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting non-secure domain
+#define IRQ_MODE_DOMAIN_SECURE      (0x01UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting secure domain
+
+#define IRQ_MODE_CPU_Pos            (5U)
+#define IRQ_MODE_CPU_Msk            (0xFFUL << IRQ_MODE_CPU_Pos)
+#define IRQ_MODE_CPU_ALL            (0x00UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets all CPUs
+#define IRQ_MODE_CPU_0              (0x01UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 0
+#define IRQ_MODE_CPU_1              (0x02UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 1
+#define IRQ_MODE_CPU_2              (0x04UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 2
+#define IRQ_MODE_CPU_3              (0x08UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 3
+#define IRQ_MODE_CPU_4              (0x10UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 4
+#define IRQ_MODE_CPU_5              (0x20UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 5
+#define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6
+#define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7
+
+#define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error
+
+/* Interrupt priority bit-masks */
+#define IRQ_PRIORITY_Msk            (0x0000FFFFUL)                    ///< Interrupt priority value bit-mask
+#define IRQ_PRIORITY_ERROR          (0x80000000UL)                    ///< Bit indicating priority value error
+
+/// Initialize interrupt controller.
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Initialize (void);
+
+/// Register interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     handler       interrupt handler function address
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
+
+/// Get the registered interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \return registered interrupt handler function address.
+IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
+
+/// Enable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Enable (IRQn_ID_t irqn);
+
+/// Disable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Disable (IRQn_ID_t irqn);
+
+/// Get interrupt enable state.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
+uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
+
+/// Configure interrupt request mode.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     mode          mode configuration
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
+
+/// Get interrupt mode configuration.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
+uint32_t IRQ_GetMode (IRQn_ID_t irqn);
+
+/// Get ID number of current interrupt request (IRQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveIRQ (void);
+
+/// Get ID number of current fast interrupt request (FIQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveFIQ (void);
+
+/// Signal end of interrupt processing.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
+
+/// Set interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPending (IRQn_ID_t irqn);
+
+/// Get interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
+uint32_t IRQ_GetPending (IRQn_ID_t irqn);
+
+/// Clear interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_ClearPending (IRQn_ID_t irqn);
+
+/// Set interrupt priority value.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     priority      interrupt priority value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
+
+/// Get interrupt priority.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
+
+/// Set priority masking threshold.
+/// \param[in]     priority      priority masking threshold value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityMask (uint32_t priority);
+
+/// Get priority masking threshold
+/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityMask (void);
+
+/// Set priority grouping field split point
+/// \param[in]     bits          number of MSB bits included in the group priority field comparison
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
+
+/// Get priority grouping field split point
+/// \return current number of MSB bits included in the group priority field comparison with
+///         optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityGroupBits (void);
+
+#endif  // IRQ_CTRL_H_

Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c

+/**************************************************************************//**
+ * @file     irq_ctrl_gic.c
+ * @brief    Interrupt controller handling implementation for GIC
+ * @version  V1.0.1
+ * @date     9. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT      (1020U)
+#endif
+
+static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+static uint32_t     IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+  uint32_t i;
+
+  for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+    IRQTable[i] = (IRQHandler_t)NULL;
+  }
+  GIC_Enable();
+  return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    IRQTable[irqn] = handler;
+    status =  0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+  IRQHandler_t h;
+
+  // Ignore CPUID field (software generated interrupts)
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    h = IRQTable[irqn];
+  } else {
+    h = (IRQHandler_t)0;
+  }
+
+  return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EnableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_DisableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+  uint32_t enable;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+  } else {
+    enable = 0U;
+  }
+
+  return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+  uint32_t val;
+  uint8_t cfg;
+  uint8_t secure;
+  uint8_t cpu;
+  int32_t status = 0;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    // Check triggering mode
+    val = (mode & IRQ_MODE_TRIG_Msk);
+
+    if (val == IRQ_MODE_TRIG_LEVEL) {
+      cfg = 0x00U;
+    } else if (val == IRQ_MODE_TRIG_EDGE) {
+      cfg = 0x02U;
+    } else {
+      cfg = 0x00U;
+      status = -1;
+    }
+
+    // Check interrupt type
+    val = mode & IRQ_MODE_TYPE_Msk;
+
+    if (val != IRQ_MODE_TYPE_IRQ) {
+      status = -1;
+    }
+
+    // Check interrupt domain
+    val = mode & IRQ_MODE_DOMAIN_Msk;
+
+    if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+      secure = 0U;
+    } else {
+      // Check security extensions support
+      val = GIC_DistributorInfo() & (1UL << 10U);
+
+      if (val != 0U) {
+        // Security extensions are supported
+        secure = 1U;
+      } else {
+        secure = 0U;
+        status = -1;
+      }
+    }
+
+    // Check interrupt CPU targets
+    val = mode & IRQ_MODE_CPU_Msk;
+
+    if (val == IRQ_MODE_CPU_ALL) {
+      cpu = 0xFFU;
+    } else {
+      cpu = val >> IRQ_MODE_CPU_Pos;
+    }
+
+    // Apply configuration if no mode error
+    if (status == 0) {
+      GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+      GIC_SetTarget       ((IRQn_Type)irqn, cpu);
+
+      if (secure != 0U) {
+        GIC_SetGroup ((IRQn_Type)irqn, secure);
+      }
+    }
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+  uint32_t mode;
+  uint32_t val;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    mode = IRQ_MODE_TYPE_IRQ;
+
+    // Get trigger mode
+    val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+    if ((val & 2U) != 0U) {
+      // Corresponding interrupt is edge triggered
+      mode |= IRQ_MODE_TRIG_EDGE;
+    } else {
+      // Corresponding interrupt is level triggered
+      mode |= IRQ_MODE_TRIG_LEVEL;
+    }
+
+    // Get interrupt CPU targets
+    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+  } else {
+    mode = IRQ_MODE_ERROR;
+  }
+
+  return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+  IRQn_ID_t irqn;
+  uint32_t prio;
+
+  /* Dummy read to avoid GIC 390 errata 801120 */
+  GIC_GetHighPendingIRQ();
+
+  irqn = GIC_AcknowledgePending();
+
+  __DSB();
+
+  /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014)  */
+  /* The following workaround code is for a single-core system.  It would be       */
+  /* different in a multi-core system.                                             */
+  /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+  /* so unlock it, otherwise service the interrupt as normal.                      */
+  /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2  */
+  /* so will not occur here.                                                       */
+
+  if ((irqn == 0) || (irqn >= 0x3FE)) {
+    /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+    prio = GIC_GetPriority((IRQn_Type)0);
+    GIC_SetPriority ((IRQn_Type)0, prio);
+
+    __DSB();
+
+    if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+      /* If the ID is 0, is active and has not been seen before */
+      IRQ_ID0 = 1U;
+    }
+    /* End of Workaround GIC 390 errata 733075 */
+  }
+
+  return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+  return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+  int32_t status;
+  IRQn_Type irq = (IRQn_Type)irqn;
+
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EndInterrupt (irq);
+
+    if (irqn == 0) {
+      IRQ_ID0 = 0U;
+    }
+
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+  uint32_t pending;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+  } else {
+    pending = 0U;
+  }
+
+  return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPriority ((IRQn_Type)irqn, priority);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+  uint32_t priority;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    priority = GIC_GetPriority ((IRQn_Type)irqn);
+  } else {
+    priority = IRQ_PRIORITY_ERROR;
+  }
+
+  return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+  GIC_SetInterfacePriorityMask (priority);
+  return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+  return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+  int32_t status;
+
+  if (bits == IRQ_PRIORITY_Msk) {
+    bits = 7U;
+  }
+
+  if (bits < 8U) {
+    GIC_SetBinaryPoint (7U - bits);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+  uint32_t bp;
+
+  bp = GIC_GetBinaryPoint() & 0x07U;
+
+  return (7U - bp);
+}
+
+#endif

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h

+#ifndef _ARR_DESC_H_
+#define _ARR_DESC_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include <stdint.h>
+#include <string.h>             /* memset() */
+#include "../util/util.h"       /* CONCAT() */
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Array-descriptor struct.
+ */
+typedef struct ARR_DESC_struct
+{
+    void *  data_ptr;                /* Pointer to the array contents. */
+    int32_t element_count;           /* Number of current elements. */
+    int32_t element_size;            /* Size of current elements in bytes. */
+    int32_t underlying_size;         /* Size of underlying array in bytes. */
+} ARR_DESC_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix of the array variable's name when creating an array and an array
+ *  descriptor at the same time.
+ */
+#define ARR_DESC_ARR_PREFIX ARR_DESC_ARR_
+
+/**
+ *  Evaluate to the array variable's name when creating an array and an array
+ *  descriptor at the same time.
+ */
+#define ARR_DESC_ARR_NAME(name)                 \
+    CONCAT(ARR_DESC_ARR_PREFIX, name)
+
+/**
+ *  Define an #ARR_DESC_t by itself.
+ *
+ *  @note The user must supply an array to store the data used by the
+ *  #ARR_DESC_t.
+ */
+#define ARR_DESC_INTERNAL_DEFINE(name, data_ptr,                \
+                                 element_count, element_size)   \
+    ARR_DESC_t name = {                                         \
+        data_ptr,                                               \
+        element_count,                                          \
+        element_size,                                           \
+        element_count * element_size                            \
+    }                                                           \
+
+/**
+ *  Define both an array and an #ARR_DESC_t that describes it.
+ *
+ *  @note Use the #CURLY() macro for the content field; it provides the curly
+ *  braces necessary for an array initialization.
+ */
+#define ARR_DESC_DEFINE(type, name, element_count, content)             \
+    type ARR_DESC_ARR_NAME(name)[element_count] = content;              \
+    ARR_DESC_INTERNAL_DEFINE(name,                                      \
+                             &ARR_DESC_ARR_NAME(name),                  \
+                             element_count,                             \
+                             sizeof(type)) /* Note the lacking semicolon */
+
+/**
+ *  Create a #ARR_DESC_t which refers to a subset of the data in another.
+ *
+ *  The new #ARR_DESC_t shares the same underlying array as the aliased
+ *  #ARR_DESC_t, but only describes a subset of the originals values.
+ */
+#define ARR_DESC_DEFINE_SUBSET(name, original, element_cnt)         \
+    ARR_DESC_INTERNAL_DEFINE(name,                                  \
+                             &ARR_DESC_ARR_NAME(original),          \
+                             element_cnt,                           \
+                             sizeof(ARR_DESC_ARR_NAME(original)[0]) \
+        ) /* Note the lacking semicolon */
+
+/**
+ *  Creat an #ARR_DESC_t which points to the data in an existing array.
+ *
+ *  @param start_idx Offset in array_ptr of first element.
+ *  @param element_cnt Number of elements to include in the #ARR_DESC_t.
+ *
+ *  @example
+ *
+ *  float my_floats[4] = {0.0f, 1.0f, 2.0f, 3.0f};
+ *
+ *  ARR_DESC_DEFINE_USING_ARR(my_arr_desc, my_floats, 1, 3);
+ *
+ *  printf("Element 0: %f\n", ARR_DESC_ELT(float, 0, &my_arr_desc));
+ *  printf("Element 1: %f\n", ARR_DESC_ELT(float, 1, &my_arr_desc));
+ *
+ *  Outputs:
+ *
+ *  Element 0: 1.000000
+ *  Element 1: 2.000000
+ *
+ *  @warning There are no checks in place to catch invalid start indices; This
+ *  is left to the user.
+ */
+#define ARR_DESC_DEFINE_USING_ARR(type, name, array_ptr, start_idx, element_cnt) \
+    ARR_DESC_INTERNAL_DEFINE(                                           \
+        name,                                                           \
+        (type *) (array_ptr + start_idx),                               \
+        element_cnt,                                                    \
+        sizeof(type)                                                    \
+        ) /* Note the lacking semicolon*/
+
+/**
+ *  Declare an #ARR_DESC_t object.
+ */
+#define ARR_DESC_DECLARE(name)                              \
+    extern ARR_DESC_t name /* Note the lacking semicolon */
+
+/**
+ *  Evaluate to the number of bytes stored in the #ARR_DESC_t.
+ */
+#define ARR_DESC_BYTES(arr_desc_ptr)                                \
+    ((arr_desc_ptr)->element_count * (arr_desc_ptr)->element_size)
+
+/**
+ *  Set the contents of #ARR_DESC_t to value.
+ */
+#define ARR_DESC_MEMSET(arr_desc_ptr, value, bytes)     \
+    do                                                  \
+    {                                                   \
+        memset((arr_desc_ptr)->data_ptr,                \
+               value,                                   \
+               BOUND(0,                                 \
+                     (arr_desc_ptr)->underlying_size,   \
+                     bytes)                             \
+            );                                          \
+    } while (0)
+
+/**
+ *  Perform a memcpy of 'bytes' bytes from the source #ARR_DESC_t to the
+ *  destination #ARR_DESC_t.
+ */
+#define ARR_DESC_MEMCPY(arr_desc_dest_ptr, arr_desc_src_ptr, bytes) \
+    do                                                              \
+    {                                                               \
+        memcpy((arr_desc_dest_ptr)->data_ptr,                       \
+               (arr_desc_src_ptr)->data_ptr,                        \
+               BOUND(0,                                             \
+                     (arr_desc_dest_ptr)->underlying_size,          \
+                     bytes));                                       \
+    } while (0)
+
+/**
+ *  Evaluate to true if the source #ARR_DESC_t contents will fit into the
+ *  destination #ARR_DESC_t and false otherwise.
+ */
+#define ARR_DESC_COPYABLE(arr_desc_dest_ptr, arr_desc_src_ptr)  \
+      (ARR_DESC_BYTES(arr_desc_src_ptr) <=                      \
+       (arr_desc_dest_ptr)->underlying_size)
+
+/**
+ *  Copy all the data from the source #ARR_DESC_t to the destination
+ *  #ARR_DESC_t.
+ *
+ *  @note If the destination #ARR_DESC_t is too small to fit the source data the
+ *  copy is aborted and nothing happens.
+ */
+#define ARR_DESC_COPY(arr_desc_dest_ptr, arr_desc_src_ptr)      \
+    do                                                          \
+    {                                                           \
+        if (ARR_DESC_COPYABLE(arr_desc_dest_ptr,                 \
+                             arr_desc_src_ptr))                 \
+        {                                                       \
+            ARR_DESC_MEMCPY(arr_desc_dest_ptr,                  \
+                            arr_desc_src_ptr,                   \
+                            ARR_DESC_BYTES(arr_desc_src_ptr));  \
+            /* Update the properties*/                          \
+            (arr_desc_dest_ptr)->element_count =                \
+                (arr_desc_src_ptr)->element_count;              \
+            (arr_desc_dest_ptr)->element_size =                 \
+                (arr_desc_src_ptr)->element_size;               \
+        }                                                       \
+    } while (0)
+
+/**
+ *  Compare the data in two #ARR_DESC_t structs for the specified number of
+ *  bytes.
+ */
+#define ARR_DESC_MEMCMP(arr_desc_ptr_a, arr_desc_ptr_b, bytes)  \
+        memcmp((arr_desc_ptr_a)->data_ptr,                      \
+            (arr_desc_ptr_b)->data_ptr,                         \
+               bytes) /* Note the lacking semicolon */          \
+
+/**
+ *  Zero out the contents of the #ARR_DESC_t.
+ */
+#define ARR_DESC_ZERO(arr_desc_ptr)             \
+        ARR_DESC_MEMSET(arr_desc_ptr,           \
+                        0,                      \
+                        (arr_desc_ptr)->underlying_size)
+
+/**
+ *  Evaluate to the data address in #ARR_DESC_t at offset.
+ */
+#define ARR_DESC_DATA_ADDR(type, arr_desc_ptr, offset)  \
+        ((void*)(((type *)                              \
+                  ((arr_desc_ptr)->data_ptr))           \
+                 + offset))
+
+/**
+ *  Evaluate to the element in #ARR_DESC_t with type at idx.
+ */
+#define ARR_DESC_ELT(type, idx, arr_desc_ptr)           \
+        (*((type *) ARR_DESC_DATA_ADDR(type,            \
+                                       arr_desc_ptr,    \
+                                       idx)))
+
+#endif /* _ARR_DESC_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h

+#ifndef _JTEST_H_
+#define _JTEST_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"
+#include "jtest_test.h"
+#include "jtest_test_define.h"
+#include "jtest_test_call.h"
+#include "jtest_group.h"
+#include "jtest_group_define.h"
+#include "jtest_group_call.h"
+#include "jtest_cycle.h"
+
+#endif /* _JTEST_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h

+#ifndef _JTEST_CYCLE_H_
+#define _JTEST_CYCLE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"           /* JTEST_DUMP_STRF() */
+#include "jtest_systick.h"
+#include "jtest_util.h"         /* STR() */
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Module Variables */
+/*--------------------------------------------------------------------------------*/
+extern const char * JTEST_CYCLE_STRF;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Wrap the function call, fn_call, to count execution cycles and display the
+ *  results.
+ */
+/* skipp function name + param
+#define JTEST_COUNT_CYCLES(fn_call)                     \
+    do                                                  \
+    {                                                   \
+        uint32_t __jtest_cycle_end_count;               \
+                                                        \
+        JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_SYSTICK_START(SysTick);                   \
+                                                        \
+        fn_call;                                        \
+                                                        \
+        __jtest_cycle_end_count =                       \
+            JTEST_SYSTICK_VALUE(SysTick);               \
+                                                        \
+		JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_DUMP_STRF(JTEST_CYCLE_STRF,               \
+                        STR(fn_call),                   \
+                        (JTEST_SYSTICK_INITIAL_VALUE -  \
+                         __jtest_cycle_end_count));     \
+    } while (0)
+*/
+#define JTEST_COUNT_CYCLES(fn_call)                     \
+    do                                                  \
+    {                                                   \
+        uint32_t __jtest_cycle_end_count;               \
+                                                        \
+        JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_SYSTICK_START(SysTick);                   \
+                                                        \
+        fn_call;                                        \
+                                                        \
+        __jtest_cycle_end_count =                       \
+            JTEST_SYSTICK_VALUE(SysTick);               \
+                                                        \
+		JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_DUMP_STRF(JTEST_CYCLE_STRF,               \
+                        (JTEST_SYSTICK_INITIAL_VALUE -  \
+                         __jtest_cycle_end_count));     \
+    } while (0)
+
+#endif /* _JTEST_CYCLE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h

+#ifndef _JTEST_DEFINE_H_
+#define _JTEST_DEFINE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Makes a symbol for use as a struct name. Names made this way have two parts;
+ *  the first parts is a prefix common to all structs of that class. The second
+ *  is a specifier which differs for each instance of that struct type.
+ */
+#define JTEST_STRUCT_NAME(prefix, specifier)    \
+    CONCAT(prefix, specifier)
+
+/**
+ *  Define a struct with type with a name generated by #JTEST_STRUCT_NAME().
+ */
+#define JTEST_DEFINE_STRUCT(type, struct_name)    \
+    type struct_name
+
+/**
+ *  Declare a struct with type with a name generated by #JTEST_STRUCT_NAME().
+ */
+#define JTEST_DECLARE_STRUCT(struct_definition) \
+    extern struct_definition
+
+/**
+ *  Define and initialize a struct (created with JTEST_DEFINE_STRUCT()) and
+ *  initialize it with init_values.
+ */
+#define JTEST_INIT_STRUCT(struct_definition, init_values)       \
+    struct_definition = {                                       \
+        init_values                                             \
+    }
+
+#endif /* _JTEST_DEFINE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h

+#ifndef _JTEST_FW_H_
+#define _JTEST_FW_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include <stdint.h>             /* int32_t */
+#include <string.h>             /* strcpy() */
+#include <stdio.h>              /* sprintf() */
+#include "jtest_pf.h"           /* Extend JTEST_FW_t with Pass/Fail data */
+#include "jtest_group.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct used to interface with the Keil Debugger.
+ */
+typedef struct JTEST_FW_struct
+{
+    /* Action Triggers: The Keil debugger monitors these values for changes.  In
+     * response to a change, the debugger executes code on the host. */
+    volatile int32_t test_start;
+    volatile int32_t test_end;
+    volatile int32_t group_start;
+    volatile int32_t group_end;
+    volatile int32_t dump_str;
+    volatile int32_t dump_data;
+    volatile int32_t exit_fw;
+
+    JTEST_GROUP_t * current_group_ptr;
+
+    /* Buffers: The C-code cannot send strings and data directly to the
+     * debugging framework. Instead, the debugger can be told to read 128 byte
+     * (by default) chunks of memory.  Data received in this manner requires
+     * post-processing to be legible.*/
+    char * str_buffer;
+    char * data_buffer;
+
+    /* Pass/Fail Data */
+    JTEST_PF_MEMBERS;
+
+} JTEST_FW_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Default name for the JTEST_FW struct.
+ *
+ *  Define your own if you want the variable containing the #JTEST_FW_t to have
+ *  a different name.
+ */
+#ifndef JTEST_FW
+#define JTEST_FW JTEST_FW
+#endif
+
+/**
+ *  Default name for the JTEST_FW_STR_BUFFER.
+ *
+ *  Define your own if you want the variable containing the char buffer to have
+ *  a different name.
+ */
+#ifndef JTEST_FW_STR_BUFFER
+#define JTEST_FW_STR_BUFFER JTEST_FW_STR_BUFFER
+#endif
+
+/**
+ *  Size of the #JTEST_FW_t, output string-buffer.
+ *
+ *  If you change this value, make sure the "dump_str_fn" and "dump_data_fn"
+ *  functions in jtest_fns.ini uses the same size. If you aren't sure, read the
+ *  documentation Keil Debugger Command 'DISPLAY'.
+ */
+#define JTEST_BUF_SIZE 256
+
+
+/**
+ *  The maximum number of bytes output at once using #JTEST_DUMP_STRF().
+ */
+#define JTEST_STR_MAX_OUTPUT_SIZE 128
+
+/**
+ *  The maximum number of block transimissions needed to send a string from a
+ *  buffer with JTEST_BUF_SIZE.
+ */
+#define JTEST_STR_MAX_OUTPUT_SEGMENTS           \
+    (JTEST_BUF_SIZE / JTEST_STR_MAX_OUTPUT_SIZE)
+
+/**
+ *  Initialize the JTEST framework.
+ */
+#define JTEST_INIT()                                                    \
+    do                                                                  \
+    {                                                                   \
+        JTEST_FW.str_buffer = JTEST_FW_STR_BUFFER;                      \
+    } while (0)
+
+/* Debugger Action-triggering Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro to trigger various actions in the Keil Debugger.
+ */
+#define JTEST_TRIGGER_ACTION(action_name)       \
+    do                                          \
+    {                                           \
+        action_name();                          \
+    } while (0)
+
+/**
+ *  Trigger the "Test Start" action in the Keil Debugger.
+ */
+#define JTEST_ACT_TEST_START()                  \
+    JTEST_TRIGGER_ACTION(test_start)
+
+/**
+ *  Trigger the "Test End" action in the Keil Debugger.
+ */
+#define JTEST_ACT_TEST_END()                    \
+    JTEST_TRIGGER_ACTION(test_end)
+
+
+/**
+ *  Trigger the "Group Start" action in the Keil Debugger.
+ */
+#define JTEST_ACT_GROUP_START()                 \
+    JTEST_TRIGGER_ACTION(group_start)
+
+/**
+ *  Trigger the "Group End" action in the Keil Debugger.
+ */
+#define JTEST_ACT_GROUP_END()                   \
+    JTEST_TRIGGER_ACTION(group_end)
+
+
+/**
+ *  Fill the buffer named buf_name with value and dump it to the Keil debugger
+ *  using action.
+ */
+#define JTEST_ACT_DUMP(action, buf_name, value) \
+    do                                          \
+    {                                           \
+        JTEST_CLEAR_BUFFER(buf_name);           \
+        strcpy(JTEST_FW.buf_name, (value));     \
+        JTEST_TRIGGER_ACTION(action);           \
+    } while (0)
+
+/**
+ *  Trigger the "Exit Framework" action in the Keil Debugger.
+ */
+#define JTEST_ACT_EXIT_FW()                     \
+    do                                          \
+    {                                           \
+        JTEST_TRIGGER_ACTION(exit_fw);          \
+    } while (0)
+
+
+/* Buffer Manipulation Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Clear the JTEST_FW buffer with name buf_name.
+ */
+#define JTEST_CLEAR_BUFFER(buf_name)                    \
+    do                                                  \
+    {                                                   \
+        memset(JTEST_FW.buf_name, 0, JTEST_BUF_SIZE);   \
+    } while (0)
+
+/**
+ *  Clear the memory needed for the JTEST_FW's string buffer.
+ */
+#define JTEST_CLEAR_STR_BUFFER()                \
+        JTEST_CLEAR_BUFFER(str_buffer)
+
+/**
+ *  Clear the memory needed for the JTEST_FW's data buffer.
+ */
+#define JTEST_CLEAR_DATA_BUFFER()               \
+        JTEST_CLEAR_BUFFER(data_buffer)
+
+/**
+ *  Dump the given string to the Keil Debugger.
+ */
+#define JTEST_DUMP_STR(string)                          \
+        JTEST_ACT_DUMP(dump_str, str_buffer, string)
+
+/**
+ *  Dump a formatted string to the Keil Debugger.
+ */
+#define JTEST_DUMP_STRF(format_str, ... )                               \
+    do                                                                  \
+    {                                                                   \
+        JTEST_CLEAR_STR_BUFFER();                                       \
+        sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__);           \
+        jtest_dump_str_segments();                                      \
+    } while (0)
+
+/* Pass/Fail Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Increment the number of passed tests in #JTEST_FW.
+ */
+#define JTEST_FW_INC_PASSED(amount)             \
+        JTEST_PF_INC_PASSED(&JTEST_FW, amount)
+
+/**
+ *  Increment the number of passed tests in #JTEST_FW.
+ */
+#define JTEST_FW_INC_FAILED(amount)             \
+        JTEST_PF_INC_FAILED(&JTEST_FW, amount)
+
+/* Manipulating the Current Group */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Evaluate to the current_group_ptr in #JTEST_FW.
+ */
+#define JTEST_CURRENT_GROUP_PTR()               \
+    (JTEST_FW.current_group_ptr)
+
+#define JTEST_SET_CURRENT_GROUP(group_ptr)      \
+    do                                          \
+    {                                           \
+        JTEST_CURRENT_GROUP_PTR() = group_ptr;  \
+    } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Global Variables */
+/*--------------------------------------------------------------------------------*/
+extern char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE];
+extern volatile JTEST_FW_t JTEST_FW;
+
+/*--------------------------------------------------------------------------------*/
+/* Function Prototypes */
+/*--------------------------------------------------------------------------------*/
+void jtest_dump_str_segments(void);
+
+void test_start  (void);
+void test_end    (void);
+void group_start (void);
+void group_end   (void);
+void dump_str    (void);
+void dump_data   (void);
+void exit_fw     (void);
+
+
+#endif /* _JTEST_FW_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h

+#ifndef _JTEST_GROUP_H_
+#define _JTEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_pf.h"
+#include "jtest_util.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct which represents a group of #JTEST_TEST_t structs. This struct is
+ *  used to run the group of tests, and report on their outcomes.
+ */
+typedef struct JTEST_GROUP_struct
+{
+    void (* group_fn_ptr) (void); /**< Pointer to the test group */
+    char * name_str;              /**< Name of the group */
+    
+    /* Extend the #JTEST_GROUP_t with Pass/Fail information.*/
+    JTEST_PF_MEMBERS;
+} JTEST_GROUP_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Set the name of JTEST_GROUP_t.
+ */
+#define JTEST_GROUP_SET_NAME(group_ptr, name)     \
+    JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, name_str, name)
+
+#define JTEST_GROUP_SET_FN(group_ptr, fn_ptr)     \
+    JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, group_fn_ptr, fn_ptr)
+
+/**
+ *  Increment the number of tests passed in the JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_INC_PASSED(group_ptr, amount) \
+    JTEST_PF_INC_PASSED(group_ptr, amount)
+
+/**
+ *  Increment the number of tests failed in the JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_INC_FAILED(group_ptr, amount) \
+    JTEST_PF_INC_FAILED(group_ptr, amount)
+
+/**
+ *  Reset the pass/fail information of the #JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_RESET_PF(group_ptr)         \
+    do                                          \
+    {                                           \
+        JTEST_PF_RESET_PASSED(group_ptr);       \
+        JTEST_PF_RESET_FAILED(group_ptr);       \
+    } while (0)
+
+#endif /* _JTEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h

+#ifndef _JTEST_GROUP_CALL_H_
+#define _JTEST_GROUP_CALL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"
+#include <inttypes.h>
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Execute the test in the #JTEST_GROUP_t struct associated witht he identifier
+ *  group_fn.
+ */
+#define JTEST_GROUP_RUN(group_fn)                                   \
+    do                                                              \
+    {                                                               \
+        JTEST_DUMP_STR("Group Name:\n");                            \
+        JTEST_DUMP_STR(JTEST_GROUP_STRUCT_NAME(group_fn).name_str); \
+        JTEST_GROUP_STRUCT_NAME(group_fn).group_fn_ptr();           \
+    } while (0)
+
+
+/**
+ *  Update the enclosing #JTEST_GROUP_t's pass/fail information using the
+ *  current #JTEST_GROUP_t's.
+ *
+ *  @param group_ptr Pointer to the current #JTEST_GROUP_t.
+ *  @param parent_ptr Pointer to the enclosing #JTEST_GROUP_t.
+ *
+ *  @warning Only run this if the current #JTEST_GROUP_t is being called within
+ *  the context of another #JTEST_GROUP_t.
+ */
+#define JTEST_GROUP_UPDATE_PARENT_GROUP_PF(group_ptr, parent_group_ptr) \
+    do                                                                  \
+    {                                                                   \
+        JTEST_GROUP_INC_PASSED(parent_group_ptr,                        \
+                               (group_ptr)->passed);                    \
+        JTEST_GROUP_INC_FAILED(parent_group_ptr,                        \
+                               (group_ptr)->failed);                    \
+    } while (0)
+
+/**
+ *  Update the #JTEST_FW's pass/fail information using the current
+ *  #JTEST_GROUP_t's.
+ */
+#define JTEST_GROUP_UPDATE_FW_PF(group_ptr)                     \
+    do                                                          \
+    {                                                           \
+        JTEST_FW_INC_PASSED((group_ptr)->passed);               \
+        JTEST_FW_INC_FAILED((group_ptr)->failed);               \
+    } while (0)
+
+/**
+ *  Update the enclosing context with the current #JTEST_GROUP_t's pass/fail
+ *  information. If this group isn't in an enclosing group, it updates the
+ *  #JTEST_FW's pass/fail info by default.
+ */
+#define JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(group_ptr,         \
+                                                 parent_group_ptr)  \
+    do                                                              \
+    {                                                               \
+        /* Update the pass fail counts in the parent group */       \
+        if (parent_group_ptr /* Null implies Top*/)                 \
+        {                                                           \
+            JTEST_GROUP_UPDATE_PARENT_GROUP_PF(                     \
+                group_ptr,                                          \
+                parent_group_ptr);                                  \
+        } else {                                                    \
+            JTEST_GROUP_UPDATE_FW_PF(                               \
+                group_ptr);                                         \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Dump the results of running the #JTEST_GROUP_t to the Keil Debugger.
+ */
+#define JTEST_GROUP_DUMP_RESULTS(group_ptr)                             \
+        do                                                              \
+        {                                                               \
+            JTEST_DUMP_STRF(                                            \
+                "Tests Run: %" PRIu32 "\n"                              \
+                "----------\n"                                          \
+                "   Passed: %" PRIu32 "\n"                              \
+                "   Failed: %" PRIu32 "\n",                             \
+                (group_ptr)->passed + (group_ptr)->failed,              \
+                (group_ptr)->passed,                                    \
+                (group_ptr)->failed);                                   \
+        } while (0)
+
+/**
+ *  Call the #JTEST_GROUP_t associated with the identifier group_fn.
+ */
+#define JTEST_GROUP_CALL(group_fn)                                      \
+        do                                                              \
+        {   /* Save the current group from JTEST_FW_t before swapping */ \
+            /* it to this group (in order to restore it later )*/       \
+            JTEST_GROUP_t * __jtest_temp_group_ptr =                    \
+                JTEST_CURRENT_GROUP_PTR();                              \
+            JTEST_SET_CURRENT_GROUP(&JTEST_GROUP_STRUCT_NAME(group_fn)); \
+                                                                        \
+            /* Reset this group's pass/fail count. Each group */        \
+            /* should only remember counts for its last execution. */   \
+            JTEST_GROUP_RESET_PF(JTEST_CURRENT_GROUP_PTR());            \
+                                                                        \
+            /* Run the current group */                                 \
+            JTEST_ACT_GROUP_START();                                    \
+            JTEST_GROUP_RUN(group_fn);                                  \
+            JTEST_ACT_GROUP_END();                                      \
+                                                                        \
+            /* Update the pass fail counts in the parent group (or FW) */ \
+            JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(                   \
+                JTEST_CURRENT_GROUP_PTR(),                              \
+                __jtest_temp_group_ptr);                                \
+                                                                        \
+            JTEST_GROUP_DUMP_RESULTS(JTEST_CURRENT_GROUP_PTR());        \
+                                                                        \
+            /* Restore the previously current group */                  \
+            JTEST_SET_CURRENT_GROUP(__jtest_temp_group_ptr);            \
+        } while (0)
+
+#endif /* _JTEST_GROUP_CALL_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h

+#ifndef _JTEST_GROUP_DEFINE_H_
+#define _JTEST_GROUP_DEFINE_H_
+
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_util.h"
+#include "jtest_define.h"
+#include "jtest_group.h"
+
+/* For defining macros with optional arguments */
+#include "opt_arg/opt_arg.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix for all #JTEST_GROUP_t structs.
+ */
+#define JTEST_GROUP_STRUCT_NAME_PREFIX G_JTEST_GROUP_STRUCT_
+
+/**
+ *  Define test template used by #JTEST_GROUP_t tests.
+ */
+#define JTEST_GROUP_FN_TEMPLATE(group_fn)    \
+    void group_fn(void)
+
+#define JTEST_GROUP_FN_PROTOTYPE JTEST_GROUP_FN_TEMPLATE /**< Alias for
+                                                            #JTEST_GROUP_FN_TEMPLATE. */
+
+/**
+ *  Evaluate to the name of the #JTEST_GROUP_t struct associated with group_fn.
+ */
+#define JTEST_GROUP_STRUCT_NAME(group_fn)    \
+    JTEST_STRUCT_NAME(JTEST_GROUP_STRUCT_NAME_PREFIX, group_fn)
+
+/**
+ *  Define a #JTEST_GROUP_t struct based on the given group_fn.
+ */
+#define JTEST_GROUP_DEFINE_STRUCT(group_fn)  \
+    JTEST_DEFINE_STRUCT(JTEST_GROUP_t,       \
+                        JTEST_GROUP_STRUCT_NAME(group_fn))
+
+/**
+ *  Declare a #JTEST_GROUP_t struct based on the given group_fn.
+ */
+#define JTEST_GROUP_DECLARE_STRUCT(group_fn) \
+    JTEST_DECLARE_STRUCT(JTEST_GROUP_DEFINE_STRUCT(group_fn))
+
+/**
+ *  Contents needed to initialize a JTEST_GROUP_t struct.
+ */
+#define JTEST_GROUP_STRUCT_INIT(group_fn)    \
+    group_fn,                                \
+        STR_NL(group_fn),                       \
+        JTEST_PF_MEMBER_INIT
+
+/**
+ *  Initialize the contents of a #JTEST_GROUP_t struct.
+ */
+#define JTEST_GROUP_INIT(group_fn)           \
+    JTEST_GROUP_DEFINE_STRUCT(group_fn) = {  \
+        JTEST_GROUP_STRUCT_INIT(group_fn)    \
+    }
+
+/* Test Definition Macro */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Define a #JTEST_GROUP_t object and a test function.
+ */
+#define JTEST_DEFINE_GROUP(group_fn)         \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn);      \
+    JTEST_GROUP_INIT(group_fn);              \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn) /* Notice the lacking semicolon */
+
+/**
+ *  Declare a #JTEST_GROUP_t object and a test function prototype.
+ */
+#define JTEST_DECLARE_GROUP(group_fn)        \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn);      \
+    JTEST_GROUP_DECLARE_STRUCT(group_fn) /* Note the lacking semicolon */
+
+#endif /* _JTEST_GROUP_DEFINE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h

+#ifndef _JTEST_PF_H_
+#define _JTEST_PF_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Purpose */
+/*--------------------------------------------------------------------------------*/
+/* jtest_pf.h Contains macros useful for capturing pass/fail data. */
+
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Members that can be added to other structs to extend them pass/fail data and
+ * corresponding functionality.
+ */
+#define JTEST_PF_MEMBERS                            \
+    uint32_t passed;                                \
+    uint32_t failed /* Note the lacking semicolon*/ \
+
+/**
+ *  Used for initializing JTEST_PF_MEMBERS in a struct declaration.
+ */
+#define JTEST_PF_MEMBER_INIT                    \
+    0,                                          \
+    0
+
+/* Member-Incrementing Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro for incrementing #JTEST_PF_MEMBERS.
+ *
+ *  @param xxx Values: 'passed', 'failed'
+ */
+#define JTEST_PF_INC_XXX(xxx, struct_pf_ptr, amount)    \
+    do                                                  \
+    {                                                   \
+        ((struct_pf_ptr)->xxx) += (amount);             \
+    } while (0)
+
+/**
+ *  Specialization of the #JTEST_PF_INC_XXX macro to increment the passed
+ *  member.
+ */
+#define JTEST_PF_INC_PASSED(struct_pf_ptr, amount)  \
+    JTEST_PF_INC_XXX(passed, struct_pf_ptr, amount)
+
+
+/**
+ *  Specialization of the #JTEST_PF_INC_XXX macro to increment the failed
+ *  member.
+ */
+#define JTEST_PF_INC_FAILED(struct_pf_ptr, amount)  \
+    JTEST_PF_INC_XXX(failed, struct_pf_ptr, amount)
+
+
+/* Member-Resetting Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro for setting #JTEST_PF_MEMBERS to zero.
+ *
+ *  @param xxx Values: 'passed', 'failed'
+ */
+#define JTEST_PF_RESET_XXX(xxx, struct_pf_ptr)  \
+    do                                          \
+    {                                           \
+        ((struct_pf_ptr)->xxx) = UINT32_C(0);   \
+    } while (0)
+
+/**
+ *  Specialization of #JTEST_PF_RESET_XXX for the 'passed' member.
+ */
+#define JTEST_PF_RESET_PASSED(struct_pf_ptr)    \
+    JTEST_PF_RESET_XXX(passed, struct_pf_ptr)
+
+/**
+ *  Specialization of #JTEST_PF_RESET_XXX for the 'failed' member.
+ */
+#define JTEST_PF_RESET_FAILED(struct_pf_ptr)    \
+    JTEST_PF_RESET_XXX(failed, struct_pf_ptr)
+
+#endif /* _JTEST_PF_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h

+#ifndef _JTEST_SYSTICK_H_
+#define _JTEST_SYSTICK_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+/* Get access to the SysTick structure. */
+#if   defined ARMCM0
+  #include "ARMCM0.h"
+#elif defined ARMCM0P
+  #include "ARMCM0plus.h"
+#elif defined ARMCM3
+  #include "ARMCM3.h"
+#elif defined ARMCM4
+  #include "ARMCM4.h"
+#elif defined ARMCM4_FP
+  #include "ARMCM4_FP.h"
+#elif defined ARMCM7
+  #include "ARMCM7.h" 
+#elif defined ARMCM7_SP
+  #include "ARMCM7_SP.h"
+#elif defined ARMCM7_DP
+  #include "ARMCM7_DP.h"
+#elif defined ARMSC000
+  #include "ARMSC000.h"
+#elif defined ARMSC300
+  #include "ARMSC300.h"
+#elif defined ARMv8MBL
+  #include "ARMv8MBL.h"
+#elif defined ARMv8MML
+  #include "ARMv8MML.h"
+#elif defined ARMv8MML_DSP
+  #include "ARMv8MML_DSP.h"
+#elif defined ARMv8MML_SP
+  #include "ARMv8MML_SP.h"
+#elif defined ARMv8MML_DSP_SP
+  #include "ARMv8MML_DSP_SP.h"
+#elif defined ARMv8MML_DP
+  #include "ARMv8MML_DP.h"
+#elif defined ARMv8MML_DSP_DP
+  #include "ARMv8MML_DSP_DP.h"
+
+#else
+  #warning "no appropriate header file found!"
+#endif
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Initial value for the SysTick module.
+ *
+ *  @note This is also the maximum value, important as SysTick is a decrementing
+ *  counter.
+ */
+#define JTEST_SYSTICK_INITIAL_VALUE 0xFFFFFF
+
+/**
+ *  Reset the SysTick, decrementing timer to it's maximum value and disable it.
+ *
+ *  This macro should leave the SysTick timer in a state that's ready for cycle
+ *  counting.
+ */
+#define JTEST_SYSTICK_RESET(systick_ptr)                    \
+    do                                                      \
+    {                                                       \
+        (systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE;  \
+        (systick_ptr)->VAL = 1;                             \
+                                                            \
+        /* Disable the SysTick module. */                   \
+        (systick_ptr)->CTRL = UINT32_C(0x000000);           \
+    } while (0)
+
+/**
+ *  Start the SysTick timer, sourced by the processor clock.
+ */
+#define JTEST_SYSTICK_START(systick_ptr)                    \
+    do                                                      \
+    {                                                       \
+        (systick_ptr)->CTRL =                               \
+            SysTick_CTRL_ENABLE_Msk |                       \
+            SysTick_CTRL_CLKSOURCE_Msk; /* Internal clk*/   \
+    } while (0)
+
+/**
+ *  Evaluate to the current value of the SysTick timer.
+ */
+#define JTEST_SYSTICK_VALUE(systick_ptr)        \
+    ((systick_ptr)->VAL)
+           
+#endif /* _JTEST_SYSTICK_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h

+#ifndef _JTEST_TEST_H_
+#define _JTEST_TEST_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include <stdint.h>
+#include "jtest_util.h"
+#include "jtest_test_ret.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct which represents a Test in the JTEST framework.  This struct is
+ *  used to enable, run, and describe the test it represents.
+ */
+typedef struct JTEST_TEST_struct
+{
+    JTEST_TEST_RET_t ( * test_fn_ptr)(void); /**< Pointer to the test function. */
+    char   * test_fn_str;                    /**< Name of the test function */
+    char   * fut_str;           /**< Name of the function under test. */
+
+    /**
+     *  Flags that govern how the #JTEST_TEST_t behaves.
+     */
+    union {
+        struct {
+            unsigned enabled : 1;
+            unsigned unused  : 7;
+        } bits;
+        uint8_t byte;           /* Access all flags at once. */
+    } flags;
+    
+} JTEST_TEST_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Assign a test function to the #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_SET_FN(jtest_test_ptr, fn_ptr)                   \
+    JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, test_fn_ptr, fn_ptr)
+
+/**
+ *  Specify a function under test (FUT) for the #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_SET_FUT(jtest_test_ptr, str)                 \
+    JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, fut_str, str)
+
+/* Macros concerning JTEST_TEST_t flags */
+/*--------------------------------------------------------------------------------*/
+
+#define JTEST_TEST_FLAG_SET 1 /**< Value of a set #JTEST_TEST_t flag. */
+#define JTEST_TEST_FLAG_CLR 0 /**< Value of a cleared #JTEST_TEST_t flag. */
+
+/**
+ *  Evaluate to the flag in #JTEST_TEST_t having flag_name.
+ */
+#define JTEST_TEST_FLAG(jtest_test_ptr, flag_name)  \
+    ((jtest_test_ptr)->flags.bits.flag_name)
+
+/**
+ *  Dispatch macro for setting and clearing #JTEST_TEST_t flags.
+ *
+ *  @param jtest_test_ptr Pointer to a #JTEST_TEST_t struct.
+ *  @param flag_name      Name of the flag to set in #JTEST_TEST_t.flags.bits
+ *  @param xxx            Vaid values: "SET" or "CLR"
+ *
+ *  @note This function depends on JTEST_TEST_FLAG_SET and JTEST_TEST_FLAG_CLR.
+ */
+#define JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, xxx)                  \
+    do                                                                       \
+    {                                                                        \
+        JTEST_TEST_FLAG(jtest_test_ptr, flag_name) = JTEST_TEST_FLAG_##xxx ; \
+    } while (0)
+
+/**
+ *  Specification of #JTEST_TEST_XXX_FLAG to set #JTEST_TEST_t flags.
+ */
+#define JTEST_TEST_SET_FLAG(jtest_test_ptr, flag_name)                       \
+    JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, SET)
+
+/**
+ *  Specification of #JTEST_TEST_XXX_FLAG to clear #JTEST_TEST_t flags.
+ */
+#define JTEST_TEST_CLR_FLAG(jtest_test_ptr, flag_name)                       \
+    JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, CLR)
+
+/**
+ *  Evaluate to true if the #JTEST_TEST_t is enabled.
+ */
+#define JTEST_TEST_IS_ENABLED(jtest_test_ptr)                           \
+    (JTEST_TEST_FLAG(jtest_test_ptr, enabled) == JTEST_TEST_FLAG_SET)
+
+#endif /* _JTEST_TEST_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h

+#ifndef _JTEST_TEST_CALL_H_
+#define _JTEST_TEST_CALL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "jtest_test.h"
+#include "jtest_test_define.h"
+#include "jtest_fw.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Exectute the test in the #JTEST_TEST_t struct associated with the identifier
+ *  test_fn and store the result in retval.
+ */
+#define JTEST_TEST_RUN(retval, test_fn)                                 \
+    do                                                                  \
+    {                                                                   \
+        JTEST_DUMP_STR("Test Name:\n");                                 \
+        JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).test_fn_str);    \
+        JTEST_DUMP_STR("Function Under Test:\n");                       \
+        JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).fut_str);        \
+        retval = JTEST_TEST_STRUCT_NAME(test_fn).test_fn_ptr();         \
+    } while (0)
+
+/**
+ *  Update the enclosing #JTEST_GROUP_t's pass/fail information based on
+ *  test_retval.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ *
+ *  @warning Only use if #JTEST_TEST_t is called in the context of a
+ *  #JTEST_GROUP_t.
+ */
+#define JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval)              \
+    do                                                              \
+    {                                                               \
+        /* Update enclosing JTEST_GROUP_t with pass/fail info */    \
+        if (test_retval == JTEST_TEST_PASSED)                       \
+        {                                                           \
+            JTEST_GROUP_INC_PASSED(JTEST_CURRENT_GROUP_PTR(), 1);   \
+        } else {                                                    \
+            JTEST_GROUP_INC_FAILED(JTEST_CURRENT_GROUP_PTR(), 1);   \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Update the #JTEST_FW with pass/fail information based on test_retval.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ */
+#define JTEST_TEST_UPDATE_FW_PF(test_retval)                        \
+    do                                                              \
+    {                                                               \
+        /* Update the JTEST_FW with pass/fail info */                \
+        if (test_retval == JTEST_TEST_PASSED)                       \
+        {                                                           \
+            JTEST_FW_INC_PASSED( 1);                                \
+        } else {                                                    \
+            JTEST_FW_INC_FAILED(1);                                 \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Update the enclosing JTEST_GROUP_t's pass/fail information, or the
+ *  #JTEST_FW's if this test has no enclosing #JTEST_GROUP_t.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ */
+#define JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(test_retval)            \
+    do                                                                  \
+    {                                                                   \
+        /* Update pass-fail information */                              \
+        if (JTEST_CURRENT_GROUP_PTR() /* Non-null */)                    \
+        {                                                               \
+            JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval);             \
+        } else {                                                        \
+            JTEST_TEST_UPDATE_FW_PF(test_retval);                       \
+        }                                                               \
+    } while (0)
+
+/**
+ *  Dump the results of the test to the Keil Debugger.
+ */
+#define JTEST_TEST_DUMP_RESULTS(test_retval)        \
+        do                                          \
+        {                                           \
+            if (test_retval == JTEST_TEST_PASSED)   \
+            {                                       \
+                JTEST_DUMP_STR("Test Passed\n");      \
+            } else {                                \
+                JTEST_DUMP_STR("Test Failed\n");      \
+            }                                       \
+        } while (0)
+
+/**
+ *  Call the #JTEST_TEST_t assocaited with the identifier test_fn.
+ */
+#define JTEST_TEST_CALL(test_fn)                                        \
+    do                                                                  \
+    {                                                                   \
+        if (JTEST_TEST_IS_ENABLED(&JTEST_TEST_STRUCT_NAME(test_fn)))    \
+        {                                                               \
+            /* Default to failure */                                    \
+            JTEST_TEST_RET_t __jtest_test_ret = JTEST_TEST_FAILED;      \
+                                                                        \
+            JTEST_ACT_TEST_START();                                     \
+            JTEST_TEST_RUN(__jtest_test_ret, test_fn);                  \
+                                                                        \
+            /* Update pass-fail information */                          \
+            JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(__jtest_test_ret);  \
+                                                                        \
+            JTEST_TEST_DUMP_RESULTS(__jtest_test_ret);                  \
+            JTEST_ACT_TEST_END();                                       \
+        }                                                               \
+    } while (0)
+
+#endif /* _JTEST_TEST_CALL_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h

+#ifndef _JTEST_TEST_DEFINE_H_
+#define _JTEST_TEST_DEFINE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_util.h"
+#include "jtest_define.h"
+#include "jtest_test.h"
+
+/* For defining macros with optional arguments */
+#include "opt_arg/opt_arg.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix for all #JTEST_TEST_t structs.
+ */
+#define JTEST_TEST_STRUCT_NAME_PREFIX G_JTEST_TEST_STRUCT_
+
+/**
+ *  Define test template used by #JTEST_TEST_t tests.
+ */
+#define JTEST_TEST_FN_TEMPLATE(test_fn)                         \
+    JTEST_TEST_RET_t test_fn(void)
+
+#define JTEST_TEST_FN_PROTOTYPE JTEST_TEST_FN_TEMPLATE /**< Alias for
+                                                        * #JTEST_TEST_FN_TEMPLATE. */
+
+/**
+ *  Evaluate to the name of the #JTEST_TEST_t struct associated with test_fn.
+ */
+#define JTEST_TEST_STRUCT_NAME(test_fn)                         \
+    JTEST_STRUCT_NAME(JTEST_TEST_STRUCT_NAME_PREFIX, test_fn)
+
+/**
+ *  Define a #JTEST_TEST_t struct based on the given test_fn.
+ */
+#define JTEST_TEST_DEFINE_STRUCT(test_fn)                   \
+    JTEST_DEFINE_STRUCT(JTEST_TEST_t,                       \
+                        JTEST_TEST_STRUCT_NAME(test_fn))
+
+/**
+ *  Declare a #JTEST_TEST_t struct based on the given test_fn.
+ */
+#define JTEST_TEST_DECLARE_STRUCT(test_fn)      \
+    JTEST_DECLARE_STRUCT(JTEST_TEST_DEFINE_STRUCT(test_fn))
+
+/**
+ *  Contents needed to initialize a JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_STRUCT_INIT(test_fn, fut, enable)    \
+    test_fn,                                            \
+        STR_NL(test_fn),                                   \
+        STR_NL(fut),                                       \
+    {                                                   \
+        {                                               \
+            enable,                                     \
+                0                                       \
+        }                                               \
+    }                                                   \
+        
+
+/**
+ *  Initialize the contents of a #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_INIT(test_fn, fut, enable)              \
+    JTEST_TEST_DEFINE_STRUCT(test_fn) = {                  \
+        JTEST_TEST_STRUCT_INIT(test_fn, fut, enable)       \
+    }
+
+/* Test Definition Macro */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Define a #JTEST_TEST_t object and a test function.
+ */
+#define _JTEST_DEFINE_TEST(test_fn, fut, enable)           \
+    JTEST_TEST_FN_PROTOTYPE(test_fn);                      \
+    JTEST_TEST_INIT(test_fn, fut, enable);                 \
+    JTEST_TEST_FN_PROTOTYPE(test_fn) /* Notice the lacking semicolon */
+
+/**
+ *  Declare a #JTEST_TEST_t object and a test function prototype.
+ */
+#define JTEST_DECLARE_TEST(test_fn)                                     \
+    JTEST_TEST_FN_PROTOTYPE(test_fn);                                   \
+    JTEST_TEST_DECLARE_STRUCT(test_fn) /* Note the lacking semicolon */
+
+/*--------------------------------------------------------------------------------*/
+/* Macros with optional arguments */
+/*--------------------------------------------------------------------------------*/
+
+/* Top-level Interface */
+#define JTEST_DEFINE_TEST(...)                             \
+    JTEST_DEFINE_TEST_(PP_NARG(__VA_ARGS__), ##__VA_ARGS__)
+
+/* Dispatch Macro*/
+#define JTEST_DEFINE_TEST_(N, ...)                         \
+    SPLICE(JTEST_DEFINE_TEST_, N)(__VA_ARGS__)
+
+/* Default Arguments */
+#define JTEST_DEFINE_TEST_DEFAULT_FUT /* Blank */
+#define JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+    JTEST_TRUE                                 /* Tests enabled by
+                                                * default. */ 
+
+/* Dispatch Cases*/
+#define JTEST_DEFINE_TEST_1(_1)                            \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        JTEST_DEFINE_TEST_DEFAULT_FUT,                     \
+        JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+        )
+
+#define JTEST_DEFINE_TEST_2(_1, _2)                        \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        _2,                                                \
+        JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+        )
+
+#define JTEST_DEFINE_TEST_3(_1, _2, _3)                    \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        _2,                                                \
+        _3                                                 \
+        )
+
+#endif /* _JTEST_TEST_DEFINE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h

+#ifndef _JTEST_TEST_RET_H_
+#define _JTEST_TEST_RET_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Values a #JTEST_TEST_t can return.
+ */
+typedef enum JTEST_TEST_RET_enum
+{
+    JTEST_TEST_PASSED,
+    JTEST_TEST_FAILED
+} JTEST_TEST_RET_t;
+
+#endif /* _JTEST_TEST_RET_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h

+#ifndef _JTEST_UTIL_H_
+#define _JTEST_UTIL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "util/util.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/* Define boolean values for the framework. */
+#define JTEST_TRUE  1           /**< Value used for TRUE in JTEST. */
+#define JTEST_FALSE 0           /**< Value used for FALSE in JTEST. */
+
+/**
+ *  Set the value of the attribute in the struct to by struct_ptr to value.
+ */
+#define JTEST_SET_STRUCT_ATTRIBUTE(struct_ptr, attribute, value)    \
+    do                                                              \
+    {                                                               \
+        (struct_ptr)->attribute = (value);                          \
+    } while (0)
+
+#endif /* _JTEST_UTIL_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h

+#ifndef _OPT_ARG_H_
+#define _OPT_ARG_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "pp_narg.h"
+#include "splice.h"
+
+/* If you are Joseph Jaoudi, you have a snippet which expands into an
+   example. If you are not Joseph, but possess his code, study the examples. If
+   you have no examples, turn back contact Joseph. */
+
+#endif /* _OPT_ARG_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h

+#ifndef _PP_NARG_H_
+#define _PP_NARG_H_
+
+#define PP_NARG(...)                                      \
+    PP_NARG_(__VA_ARGS__,PP_RSEQ_N())
+#define PP_NARG_(...)                                     \
+    PP_ARG_N(__VA_ARGS__)
+#define PP_ARG_N(                                         \
+                 _1, _2, _3, _4, _5, _6, _7, _8, _9,_10,  \
+                 _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
+                 _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
+                 _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
+                 _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
+                 _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
+                 _61,_62,_63,N,...) N
+#define PP_RSEQ_N()                                       \
+    63,62,61,60,                                          \
+        59,58,57,56,55,54,53,52,51,50,                    \
+        49,48,47,46,45,44,43,42,41,40,                    \
+        39,38,37,36,35,34,33,32,31,30,                    \
+        29,28,27,26,25,24,23,22,21,20,                    \
+        19,18,17,16,15,14,13,12,11,10,                    \
+        9,8,7,6,5,4,3,2,1,0
+
+#endif /* _PP_NARG_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h

+#ifndef _SPLICE_H_
+#define _SPLICE_H_
+
+#define SPLICE(a,b) SPLICE_1(a,b)
+#define SPLICE_1(a,b) SPLICE_2(a,b)
+#define SPLICE_2(a,b) a##b
+
+#endif /* _SPLICE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h

+#ifndef _UTIL_H_
+#define _UTIL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Convert a symbol to a string and add a 'NewLine'.
+ */
+#define STR_NL(x)  STR1_NL(x)
+#define STR1_NL(x) (STR2_NL(x)"\n")
+#define STR2_NL(x) #x
+
+/**
+ *  Convert a symbol to a string.
+ */
+#define STR(x)  STR1(x)
+#define STR1(x) STR2(x)
+#define STR2(x) #x
+
+/**
+ *  Concatenate two symbols.
+ */
+#define CONCAT(a, b)  CONCAT1(a, b)
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define CONCAT2(a, b) a##b
+
+
+/**
+ *  Place curly braces around a varaible number of macro arguments.
+ */
+#define CURLY(...) {__VA_ARGS__}
+
+/**
+ *  Place parenthesis around a variable number of macro arguments.
+ */
+#define PAREN(...) (__VA_ARGS__)
+
+/* Standard min/max macros. */
+#define MIN(x,y) (((x) < (y)) ? (x) : (y) )
+#define MAX(x,y) (((x) > (y)) ? (x) : (y) )
+
+/**
+ *  Bound value using low and high limits.
+ *
+ *  Evaluate to a number in the range, endpoint inclusive.
+ */
+#define BOUND(low, high, value)                 \
+    MAX(MIN(high, value), low)
+
+#endif /* _UTIL_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c

+#include "../inc/jtest_cycle.h"
+#include <inttypes.h>
+
+/*--------------------------------------------------------------------------------*/
+/* Define Module Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* const char * JTEST_CYCLE_STRF = "Running: %s\nCycles: %" PRIu32 "\n"; */
+const char * JTEST_CYCLE_STRF = "Cycles: %" PRIu32 "\n"; /* function name + parameter string skipped */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c

+#include "jtest_fw.h"
+
+/**
+ *  Dump the JTEST_FW.str_buffer the Keil framework in pieces.
+ *
+ *  The JTEST_FW.str_buffer contains more characters than the Keil framework can
+ *  dump at once. This function dumps them in blocks.
+ */
+void jtest_dump_str_segments(void)
+{
+    uint32_t seg_idx      = 0;
+    uint32_t memmove_idx = 0;
+    uint32_t seg_cnt  =
+        (strlen(JTEST_FW.str_buffer) / JTEST_STR_MAX_OUTPUT_SIZE) + 1;
+
+    for( seg_idx = 0; seg_idx < seg_cnt; ++seg_idx)
+    {
+        JTEST_TRIGGER_ACTION(dump_str);
+
+        if (seg_idx < JTEST_STR_MAX_OUTPUT_SEGMENTS)
+        {
+            memmove_idx = 0;
+            while (memmove_idx < (seg_cnt - seg_idx -1) )
+            {
+                memmove(
+                    JTEST_FW.str_buffer+
+                    (memmove_idx* JTEST_STR_MAX_OUTPUT_SIZE),
+                    JTEST_FW.str_buffer+
+                    ((memmove_idx+1)*JTEST_STR_MAX_OUTPUT_SIZE),
+                    JTEST_BUF_SIZE);
+                ++memmove_idx;
+            }
+        }
+    }
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c

+#include "../inc/jtest.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Define Global Variables */
+/*--------------------------------------------------------------------------------*/
+
+char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE] = {0};
+
+volatile JTEST_FW_t JTEST_FW = {0};

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c

+
+#include "jtest_fw.h"
+
+void test_start    (void) {
+//  ;
+  JTEST_FW.test_start++;
+}
+
+void test_end      (void) {
+//  ;
+  JTEST_FW.test_end++;
+}
+
+void group_start   (void) {
+//  ;
+  JTEST_FW.group_start++;
+}
+
+void group_end     (void) {
+//  ;
+  JTEST_FW.group_end++;
+}
+
+void dump_str      (void) {
+//  ;
+  JTEST_FW.dump_str++;
+}
+
+void dump_data     (void) {
+//  ;
+  JTEST_FW.dump_data++;
+}
+
+void exit_fw       (void) {
+//  ;
+  JTEST_FW.exit_fw++;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h

+#ifndef _ALL_TESTS_H_
+#define _ALL_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(all_tests);
+
+#endif /* _ALL_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h

+#ifndef _BASIC_MATH_TEMPLATES_H_
+#define _BASIC_MATH_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Compare the outputs used by basic math tests for the function under test and
+ *  the reference function.
+ */
+#define BASIC_MATH_COMPARE_INTERFACE(block_size, output_type)   \
+    TEST_ASSERT_BUFFERS_EQUAL(                                  \
+        basic_math_output_ref.data_ptr,                         \
+        basic_math_output_fut.data_ptr,                         \
+        block_size * sizeof(output_type))
+
+/*
+ * Comparison SNR thresholds for the data types used in basic_math_tests.
+ */
+#define BASIC_MATH_SNR_THRESHOLD_float32_t 120
+#define BASIC_MATH_SNR_THRESHOLD_q31_t 100
+#define BASIC_MATH_SNR_THRESHOLD_q15_t 75
+#define BASIC_MATH_SNR_THRESHOLD_q7_t 25
+
+/**
+ *  Compare reference and fut outputs using SNR.
+ *
+ *  @note The outputs are converted to float32_t before comparison.
+ */
+#define BASIC_MATH_SNR_COMPARE_INTERFACE(block_size, output_type)   \
+    do                                                              \
+    {                                                               \
+        TEST_CONVERT_AND_ASSERT_SNR(                                \
+            basic_math_output_f32_ref,                              \
+            basic_math_output_ref.data_ptr,                         \
+            basic_math_output_f32_fut,                              \
+            basic_math_output_fut.data_ptr,                         \
+            block_size,                                             \
+            output_type,                                            \
+            BASIC_MATH_SNR_THRESHOLD_##output_type                  \
+            );                                                      \
+    } while (0)
+
+
+/**
+ *  Compare reference and fut outputs using SNR.
+ *
+ *  @note The outputs are converted to float32_t before comparison.
+ */
+#define BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE(block_size, output_type)  \
+    do                                                                  \
+    {                                                                   \
+        TEST_CONVERT_AND_ASSERT_SNR(                                    \
+            basic_math_output_f32_ref,                                  \
+            basic_math_output_ref.data_ptr,                             \
+            basic_math_output_f32_fut,                                  \
+            basic_math_output_fut.data_ptr,                             \
+            1,                                                          \
+            output_type,                                                \
+            BASIC_MATH_SNR_THRESHOLD_##output_type                      \
+            );                                                          \
+    } while (0)
+
+
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define ARM_abs_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, basic_math_output_fut.data_ptr, block_size)
+
+#define REF_abs_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, basic_math_output_ref.data_ptr, block_size)
+
+#define ARM_add_INPUT_INTERFACE(input_a, input_b, block_size)           \
+    PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_add_INPUT_INTERFACE(input_a, input_b, block_size)           \
+    PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size)      \
+    PAREN(input_a, input_b, block_size, basic_math_output_fut.data_ptr) \
+
+#define REF_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size)      \
+    PAREN(input_a, input_b, block_size, basic_math_output_ref.data_ptr) \
+
+#define ARM_mult_INPUT_INTERFACE(input_a, input_b, block_size)          \
+    PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_mult_INPUT_INTERFACE(input_a, input_b, block_size)          \
+    PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_negate_INPUT_INTERFACE(input, block_size)           \
+    PAREN(input, basic_math_output_fut.data_ptr, block_size)
+
+#define REF_negate_INPUT_INTERFACE(input, block_size)           \
+    PAREN(input, basic_math_output_ref.data_ptr, block_size)
+
+#define ARM_offset_INPUT_INTERFACE(input, elt, block_size)          \
+    PAREN(input, elt, basic_math_output_fut.data_ptr, block_size)   \
+
+#define REF_offset_INPUT_INTERFACE(input, elt, block_size)          \
+    PAREN(input, elt, basic_math_output_ref.data_ptr, block_size)   \
+
+#define ARM_shift_INPUT_INTERFACE(input, elt, block_size)           \
+    PAREN(input, elt, basic_math_output_fut.data_ptr, block_size)   \
+
+#define REF_shift_INPUT_INTERFACE(input, elt, block_size)           \
+    PAREN(input, elt, basic_math_output_ref.data_ptr, block_size)   \
+
+#define ARM_scale_float_INPUT_INTERFACE(input, elt, block_size)     \
+    PAREN(input, elt, basic_math_output_fut.data_ptr, block_size)   \
+
+#define REF_scale_float_INPUT_INTERFACE(input, elt, block_size)     \
+    PAREN(input, elt, basic_math_output_ref.data_ptr, block_size)   \
+
+/* These two are for the fixed point functions */
+#define ARM_scale_INPUT_INTERFACE(input, elt1, elt2, block_size)        \
+    PAREN(input, elt1, elt2, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_scale_INPUT_INTERFACE(input, elt1, elt2, block_size)        \
+    PAREN(input, elt1, elt2, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_sub_INPUT_INTERFACE(input_a, input_b, block_size)           \
+    PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_sub_INPUT_INTERFACE(input_a, input_b, block_size)           \
+    PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_BLK() for basic math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name,       \
+                                                 suffix,        \
+                                                 input_type,    \
+                                                 output_type)   \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,          \
+                      arm_##fn_name##_##suffix)                 \
+    {                                                           \
+        TEST_TEMPLATE_BUF1_BLK(                                 \
+            basic_math_f_all,                                   \
+            basic_math_block_sizes,                             \
+            input_type,                                         \
+            output_type,                                        \
+            arm_##fn_name##_##suffix,                           \
+            ARM_##fn_name##_INPUT_INTERFACE,                    \
+            ref_##fn_name##_##suffix,                           \
+            REF_##fn_name##_INPUT_INTERFACE,                    \
+            BASIC_MATH_COMPARE_INTERFACE);                      \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF2_BLK() for basic math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name,               \
+                                                 suffix,                \
+                                                 input_type,            \
+                                                 output_type,           \
+                                                 comparison_interface)  \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,                  \
+                      arm_##fn_name##_##suffix)                         \
+    {                                                                   \
+        TEST_TEMPLATE_BUF2_BLK(                                         \
+            basic_math_f_all,                                           \
+            basic_math_f_all,                                           \
+            basic_math_block_sizes,                                     \
+            input_type,                                                 \
+            output_type,                                                \
+            arm_##fn_name##_##suffix,                                   \
+            ARM_##fn_name##_INPUT_INTERFACE,                            \
+            ref_##fn_name##_##suffix,                                   \
+            REF_##fn_name##_INPUT_INTERFACE,                            \
+            comparison_interface);                                      \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_ELT1_BLK() for basic math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK(fn_name,      \
+                                                      suffix,       \
+                                                      input_type,   \
+                                                      elt_type,     \
+                                                      output_type)  \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF1_ELT1_BLK(                                \
+            basic_math_f_all,                                       \
+            basic_math_elts,                                        \
+            basic_math_block_sizes,                                 \
+            input_type,                                             \
+            elt_type,                                               \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            BASIC_MATH_COMPARE_INTERFACE);                          \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_ELT2_BLK() for basic math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK(fn_name,      \
+                                                      suffix,       \
+                                                      input_type,   \
+                                                      elt1_type,    \
+                                                      elt2_type,    \
+                                                      output_type)  \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF1_ELT2_BLK(                                \
+            basic_math_f_all,                                       \
+            basic_math_elts,                                        \
+            basic_math_elts2,                                       \
+            basic_math_block_sizes,                                 \
+            input_type,                                             \
+            elt1_type,                                              \
+            elt2_type,                                              \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            BASIC_MATH_COMPARE_INTERFACE);                          \
+    }
+
+#endif /* _BASIC_MATH_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h

+#ifndef ARM_BASIC_MATH_TEST_DATA_H
+#define ARM_BASIC_MATH_TEST_DATA_H
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define BASIC_MATH_MAX_INPUT_ELEMENTS 32
+#define BASIC_MATH_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(basic_math_output_fut);
+ARR_DESC_DECLARE(basic_math_output_ref);
+
+extern BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+extern BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+/* Block Sizes*/
+ARR_DESC_DECLARE(basic_math_block_sizes);
+
+/* Numbers */
+ARR_DESC_DECLARE(basic_math_elts);
+ARR_DESC_DECLARE(basic_math_elts2);
+ARR_DESC_DECLARE(basic_math_eltsf);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(basic_math_zeros);
+ARR_DESC_DECLARE(basic_math_f_2);
+ARR_DESC_DECLARE(basic_math_f_15);
+ARR_DESC_DECLARE(basic_math_f_32);
+ARR_DESC_DECLARE(basic_math_f_all);
+
+#endif

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h

+#ifndef _BASIC_MATH_TEST_GROUP_H_
+#define _BASIC_MATH_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(basic_math_tests);
+
+#endif /* _BASIC_MATH_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h

+#ifndef _BASIC_MATH_TESTS_H_
+#define _BASIC_MATH_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(abs_tests);
+JTEST_DECLARE_GROUP(add_tests);
+JTEST_DECLARE_GROUP(dot_prod_tests);
+JTEST_DECLARE_GROUP(mult_tests);
+JTEST_DECLARE_GROUP(negate_tests);
+JTEST_DECLARE_GROUP(offset_tests);
+JTEST_DECLARE_GROUP(scale_tests);
+JTEST_DECLARE_GROUP(shift_tests);
+JTEST_DECLARE_GROUP(sub_tests);
+
+#endif /* _BASIC_MATH_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h

+#ifndef _COMPLEX_MATH_TEMPLATES_H_
+#define _COMPLEX_MATH_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Compare the real outputs from the function under test and the reference
+ *  function.
+ */
+#define COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size, output_type)  \
+    TEST_ASSERT_BUFFERS_EQUAL(                                      \
+        complex_math_output_ref_a.data_ptr,                         \
+        complex_math_output_fut_a.data_ptr,                         \
+        block_size * sizeof(output_type))
+
+/**
+ *  Compare the real and imaginary outputs from the function under test and the
+ *  reference function.
+ */
+#define COMPLEX_MATH_COMPARE_CMPLX_INTERFACE(block_size, output_type)   \
+    do                                                                  \
+    {                                                                   \
+        COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size * 2, output_type); \
+    } while (0)
+
+
+/*
+ * Comparison SNR thresholds for the data types used in complex_math_tests.
+ */
+#define COMPLEX_MATH_SNR_THRESHOLD_float32_t 120
+#define COMPLEX_MATH_SNR_THRESHOLD_q31_t 100
+#define COMPLEX_MATH_SNR_THRESHOLD_q15_t 75
+
+/**
+ *  Compare reference and fut outputs using SNR.
+ *
+ *  The output_suffix specifies which output buffers to use for the
+ *  comparison. An output_suffix of 'a' expands to the following buffers:
+ *
+ *  - complex_math_output_f32_ref_a
+ *  - complex_math_output_f32_fut_a
+ *  - complex_math_output_ref_a
+ *  - complex_math_output_fut_a
+ *
+ *  @note The outputs are converted to float32_t before comparison.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size,      \
+                                               output_type,     \
+                                               output_suffix)   \
+    do                                                          \
+    {                                                           \
+        TEST_CONVERT_AND_ASSERT_SNR(                            \
+            complex_math_output_f32_ref_##output_suffix,        \
+            complex_math_output_ref_##output_suffix.data_ptr,   \
+            complex_math_output_f32_fut_##output_suffix,        \
+            complex_math_output_fut_##output_suffix.data_ptr,   \
+            block_size,                                         \
+            output_type,                                        \
+            COMPLEX_MATH_SNR_THRESHOLD_##output_type            \
+            );                                                  \
+    } while (0)
+
+/**
+ *  Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for real outputs.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE(block_size,       \
+                                                   output_type) \
+    COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size,          \
+                                           output_type,         \
+                                           a)
+
+/**
+ *  Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for complex outputs.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE(block_size,    \
+                                                 output_type)   \
+        COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size * 2,  \
+                                               output_type,     \
+                                               a)
+
+/**
+ *  Compare reference and fut split outputs using SNR.
+ *
+ *  'Split' refers to two separate output buffers; one for real and one for
+ *  complex.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE(block_size,    \
+                                                 output_type)   \
+        do                                                      \
+        {                                                       \
+            COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size,  \
+                                                   output_type, \
+                                                   a);          \
+            COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size,  \
+                                                   output_type, \
+                                                   b);          \
+        } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define ARM_cmplx_conj_INPUT_INTERFACE(input, block_size)           \
+    PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_conj_INPUT_INTERFACE(input, block_size)           \
+    PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, block_size,                                 \
+          complex_math_output_fut_a.data_ptr,                          \
+          complex_math_output_fut_b.data_ptr)
+
+#define REF_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, block_size,                                 \
+          complex_math_output_ref_a.data_ptr,                          \
+          complex_math_output_ref_b.data_ptr)
+
+#define ARM_cmplx_mag_INPUT_INTERFACE(input, block_size)            \
+    PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mag_INPUT_INTERFACE(input, block_size)            \
+    PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mag_squared_INPUT_INTERFACE(input, block_size)    \
+    PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mag_squared_INPUT_INTERFACE(input, block_size)    \
+    PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size)
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_BLK() for complex math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name,         \
+                                                   suffix,          \
+                                                   input_type,      \
+                                                   output_type,     \
+                                                   comparison_interface) \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF1_BLK(                                     \
+            complex_math_f_all,                                     \
+            complex_math_block_sizes,                               \
+            input_type,                                             \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            comparison_interface);                                  \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF2_BLK1() for complex math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name,         \
+                                                   suffix,          \
+                                                   input_type,      \
+                                                   output_type,     \
+                                                   comparison_interface) \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF2_BLK(                                     \
+            complex_math_f_all,                                     \
+            complex_math_f_all,                                     \
+            complex_math_block_sizes,                               \
+            input_type,                                             \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            comparison_interface);                                  \
+    }
+
+#endif /* _COMPLEX_MATH_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h

+#ifndef _COMPLEX_MATH_TEST_DATA_H_
+#define _COMPLEX_MATH_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define COMPLEX_MATH_MAX_INPUT_ELEMENTS 32
+#define COMPLEX_MATH_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Decalare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(complex_math_output_fut_a);
+ARR_DESC_DECLARE(complex_math_output_fut_b);
+ARR_DESC_DECLARE(complex_math_output_ref_a);
+ARR_DESC_DECLARE(complex_math_output_ref_b);
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+/* Block Sizes*/
+ARR_DESC_DECLARE(complex_math_block_sizes);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(complex_math_zeros);
+ARR_DESC_DECLARE(complex_math_f_2);
+ARR_DESC_DECLARE(complex_math_f_15);
+ARR_DESC_DECLARE(complex_math_f_32);
+ARR_DESC_DECLARE(complex_math_f_all);
+
+
+#endif /* _COMPLEX_MATH_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h

+#ifndef _COMPLEX_MATH_TEST_GROUP_H_
+#define _COMPLEX_MATH_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(complex_math_tests);
+
+#endif /* _COMPLEX_MATH_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h

+#ifndef _COMPLEX_MATH_TESTS_H_
+#define _COMPLEX_MATH_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(cmplx_conj_tests);
+JTEST_DECLARE_GROUP(cmplx_dot_prod_tests);
+JTEST_DECLARE_GROUP(cmplx_mag_tests);
+JTEST_DECLARE_GROUP(cmplx_mag_squared_tests);
+JTEST_DECLARE_GROUP(cmplx_mult_cmplx_tests);
+JTEST_DECLARE_GROUP(cmplx_mult_real_tests);
+
+#endif /* _COMPLEX_MATH_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h

+#ifndef _CONTROLLER_TEMPLATES_H_
+#define _CONTROLLER_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h>             /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Comparison SNR thresholds for the data types used in transform_tests.
+ */
+#define CONTROLLER_SNR_THRESHOLD_float32_t 110
+#define CONTROLLER_SNR_THRESHOLD_q31_t     100
+#define CONTROLLER_SNR_THRESHOLD_q15_t     45
+
+/**
+ *  Compare the outputs from the function under test and the reference
+ *  function using SNR.
+ */
+#define CONTROLLER_SNR_COMPARE_INTERFACE(block_size,    \
+                                         output_type)   \
+    do                                                  \
+    {                                                   \
+        TEST_CONVERT_AND_ASSERT_SNR(                    \
+            controller_output_f32_ref,                  \
+            (output_type *) controller_output_ref,      \
+            controller_output_f32_fut,                  \
+            (output_type *) controller_output_fut,      \
+            block_size,                                 \
+            output_type,                                \
+            CONTROLLER_SNR_THRESHOLD_##output_type      \
+            );                                          \
+    } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#endif /* _CONTROLLER_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h

+#ifndef _CONTROLLER_TEST_DATA_H_
+#define _CONTROLLER_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define CONTROLLER_MAX_LEN 1024
+#define CONTROLLER_MAX_COEFFS_LEN (12 * 3)
+#define TRANFORM_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+extern float32_t controller_output_fut[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_ref[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN];
+extern const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN];
+extern const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN];
+extern const q15_t * controller_q15_inputs;
+extern const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+extern const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+extern const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+
+#endif /* _CONTROLLER_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h

+#ifndef _CONTROLLER_TEST_GROUP_H_
+#define _CONTROLLER_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Group */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(controller_tests);
+
+#endif /* _CONTROLLER_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h

+#ifndef _CONTROLLER_TESTS_H_
+#define _CONTROLLER_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(pid_reset_tests);
+JTEST_DECLARE_GROUP(sin_cos_tests);
+JTEST_DECLARE_GROUP(pid_tests);
+
+#endif /* _CONTROLLER_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_templates.h

+#ifndef _FAST_MATH_TEMPLATES_H_
+#define _FAST_MATH_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h>             /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Comparison SNR thresholds for the data types used in transform_tests.
+ */
+#define FAST_MATH_SNR_THRESHOLD_float32_t 95
+#define FAST_MATH_SNR_THRESHOLD_q31_t     95
+#define FAST_MATH_SNR_THRESHOLD_q15_t     45
+
+/**
+ *  Compare the outputs from the function under test and the reference
+ *  function using SNR.
+ */
+#define FAST_MATH_SNR_COMPARE_INTERFACE(block_size,     \
+                                        output_type)    \
+    do                                                  \
+    {                                                   \
+        TEST_CONVERT_AND_ASSERT_SNR(                    \
+            fast_math_output_f32_ref,                   \
+            (output_type *) fast_math_output_ref,       \
+            fast_math_output_f32_fut,                   \
+            (output_type *) fast_math_output_fut,       \
+            block_size,                                 \
+            output_type,                                \
+            FAST_MATH_SNR_THRESHOLD_##output_type       \
+            );                                          \
+    } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#define SQRT_TEST_TEMPLATE_ELT1(suffix)                             \
+                                                                    \
+    JTEST_DEFINE_TEST(arm_sqrt_##suffix##_test, arm_sqrt_##suffix)  \
+    {                                                               \
+        uint32_t i;                                                 \
+                                                                    \
+        JTEST_COUNT_CYCLES(                                         \
+            for(i=0;i<FAST_MATH_MAX_LEN;i++)                        \
+            {                                                       \
+                arm_sqrt_##suffix(                                  \
+                    (suffix##_t)fast_math_##suffix##_inputs[i]      \
+                    ,(suffix##_t*)fast_math_output_fut + i);        \
+            });                                                     \
+                                                                    \
+        for(i=0;i<FAST_MATH_MAX_LEN;i++)                            \
+        {                                                           \
+            ref_sqrt_##suffix(                                      \
+                (suffix##_t)fast_math_##suffix##_inputs[i]          \
+                ,(suffix##_t*)fast_math_output_ref + i);            \
+        }                                                           \
+                                                                    \
+        FAST_MATH_SNR_COMPARE_INTERFACE(                            \
+            FAST_MATH_MAX_LEN,                                      \
+            suffix##_t);                                            \
+                                                                    \
+        return JTEST_TEST_PASSED;                                   \
+    }
+
+
+#define SIN_COS_TEST_TEMPLATE_ELT1(suffix, type, func)                  \
+                                                                        \
+        JTEST_DEFINE_TEST(arm_##func##_##suffix##_test, arm_##func##_##suffix) \
+        {                                                               \
+            uint32_t i;                                                 \
+                                                                        \
+            JTEST_COUNT_CYCLES(                                         \
+                for(i=0;i<FAST_MATH_MAX_LEN;i++)                        \
+                {                                                       \
+                    *((type*)fast_math_output_fut + i) = arm_##func##_##suffix( \
+                        fast_math_##suffix##_inputs[i]);                \
+                });                                                     \
+                                                                        \
+            JTEST_COUNT_CYCLES(                                         \
+                for(i=0;i<FAST_MATH_MAX_LEN;i++)                        \
+                {                                                       \
+                    *((type*)fast_math_output_ref + i) = ref_##func##_##suffix( \
+                        fast_math_##suffix##_inputs[i]);                \
+                });                                                     \
+                                                                        \
+            FAST_MATH_SNR_COMPARE_INTERFACE(                            \
+                FAST_MATH_MAX_LEN,                                      \
+                type);                                                  \
+                                                                        \
+            return JTEST_TEST_PASSED;                                   \
+        }
+
+#endif /* _FAST_MATH_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_test_data.h

+#ifndef _FAST_MATH_TEST_DATA_H_
+#define _FAST_MATH_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define FAST_MATH_MAX_LEN 1024
+#define TRANFORM_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+extern float32_t fast_math_output_fut[FAST_MATH_MAX_LEN];
+extern float32_t fast_math_output_ref[FAST_MATH_MAX_LEN];
+extern float32_t fast_math_output_f32_fut[FAST_MATH_MAX_LEN];
+extern float32_t fast_math_output_f32_ref[FAST_MATH_MAX_LEN];
+extern const float32_t fast_math_f32_inputs[FAST_MATH_MAX_LEN];
+extern const q31_t fast_math_q31_inputs[FAST_MATH_MAX_LEN];
+extern const q15_t * fast_math_q15_inputs;
+
+#endif /* _FAST_MATH_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/fast_math_tests/fast_math_test_group.h

+#ifndef _FAST_MATH_TEST_GROUP_H_
+#define _FAST_MATH_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(fast_math_tests);
+
+#endif /* _FAST_MATH_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_templates.h

+#ifndef _FILTERING_TEMPLATES_H_
+#define _FILTERING_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ * Comparison SNR thresholds for the data types used in statistics_tests.
+ */
+#define FILTERING_SNR_THRESHOLD_float64_t 120
+#define FILTERING_SNR_THRESHOLD_float32_t 99
+#define FILTERING_SNR_THRESHOLD_q31_t 90
+#define FILTERING_SNR_THRESHOLD_q15_t 60
+#define FILTERING_SNR_THRESHOLD_q7_t 30
+
+/**
+ *  Compare reference and fut outputs using SNR.
+ *
+ *  @note The outputs are converted to float32_t before comparison.
+ */
+#define FILTERING_SNR_COMPARE_INTERFACE(block_size,                     \
+                                        output_type)                    \
+    FILTERING_SNR_COMPARE_INTERFACE_OFFSET(0, block_size, output_type)
+
+/**
+ *  Compare reference and fut outputs starting at some offset using SNR.
+ */
+#define FILTERING_SNR_COMPARE_INTERFACE_OFFSET(offset,      \
+                                               block_size,  \
+                                               output_type) \
+    do                                                      \
+    {                                                       \
+        TEST_CONVERT_AND_ASSERT_SNR(                        \
+            filtering_output_f32_ref,                       \
+            (output_type *) filtering_output_ref + offset,  \
+            filtering_output_f32_fut,                       \
+            (output_type *) filtering_output_fut + offset,  \
+            block_size,                                     \
+            output_type,                                    \
+            FILTERING_SNR_THRESHOLD_##output_type           \
+            );                                              \
+    } while (0)                                              
+
+/**
+ *  Compare reference and fut outputs starting at some offset using SNR.
+ *  Special case for float64_t
+ */
+#define FILTERING_DBL_SNR_COMPARE_INTERFACE(block_size,  				\
+                                            output_type) 				\
+    do                                                      		\
+    {                                                       		\
+        TEST_ASSERT_DBL_SNR(                        						\
+            (float64_t*)filtering_output_ref,               \
+            (float64_t*)filtering_output_fut,               \
+            block_size,                                     		\
+            FILTERING_SNR_THRESHOLD_##output_type           		\
+            );                                              		\
+    } while (0)                                              
+		
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+
+
+#endif /* _FILTERING_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_data.h

+#ifndef FILTERING_TEST_DATA_H
+#define FILTERING_TEST_DATA_H
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define FILTERING_MAX_BLOCKSIZE  33
+#define LMS_MAX_BLOCKSIZE        512
+#define FILTERING_MAX_NUMTAPS		34
+#define FILTERING_MAX_NUMSTAGES  14
+#define FILTERING_MAX_POSTSHIFT  8
+#define FILTERING_MAX_TAP_DELAY	0xFF
+#define FILTERING_MAX_L				3
+#define FILTERING_MAX_M				33
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+extern float32_t filtering_output_fut[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_output_ref[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_output_f32_fut[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_output_f32_ref[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_input_lms[LMS_MAX_BLOCKSIZE*2];
+extern float32_t filtering_pState[LMS_MAX_BLOCKSIZE + FILTERING_MAX_NUMTAPS];
+extern float32_t filtering_scratch[FILTERING_MAX_BLOCKSIZE * 3];
+extern float32_t filtering_scratch2[FILTERING_MAX_BLOCKSIZE * 3];
+extern float32_t filtering_coeffs_lms[FILTERING_MAX_NUMTAPS];
+
+extern const float64_t filtering_f64_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS];
+extern const float32_t filtering_f32_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS];
+extern const q31_t filtering_q31_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS];
+extern const q15_t * filtering_q15_inputs;
+extern const q7_t * filtering_q7_inputs;
+
+/* Block Sizes */
+ARR_DESC_DECLARE(filtering_blocksizes);
+ARR_DESC_DECLARE(lms_blocksizes);
+ARR_DESC_DECLARE(filtering_numtaps);
+ARR_DESC_DECLARE(filtering_numtaps2);
+ARR_DESC_DECLARE(filtering_postshifts);
+ARR_DESC_DECLARE(filtering_numstages);
+ARR_DESC_DECLARE(filtering_Ls);
+ARR_DESC_DECLARE(filtering_Ms);
+
+/* Coefficient Lists */
+extern const float64_t filtering_coeffs_f64[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const float64_t filtering_coeffs_b_f64[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const float32_t filtering_coeffs_f32[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const float32_t filtering_coeffs_b_f32[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const float32_t *filtering_coeffs_c_f32;
+extern float32_t filtering_coeffs_lms_f32[FILTERING_MAX_NUMTAPS];
+extern const q31_t filtering_coeffs_q31[FILTERING_MAX_NUMSTAGES * 6 + 2];
+extern const q31_t *filtering_coeffs_b_q31;
+extern const q31_t *filtering_coeffs_c_q31;
+extern q31_t filtering_coeffs_lms_q31[FILTERING_MAX_NUMTAPS];
+extern const q15_t filtering_coeffs_q15[FILTERING_MAX_NUMSTAGES * 6 + 4];
+extern const q15_t *filtering_coeffs_b_q15;
+extern const q15_t *filtering_coeffs_c_q15;
+extern q15_t filtering_coeffs_lms_q15[FILTERING_MAX_NUMTAPS];
+extern const q7_t filtering_coeffs_q7[FILTERING_MAX_NUMSTAGES * 6 + 8];
+extern const q7_t *filtering_coeffs_b_q7;
+extern const q7_t *filtering_coeffs_c_q7;
+
+/* Tap Delay Lists */
+extern const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS];
+
+/* Numbers */
+
+/* Float Inputs */
+
+#endif

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_test_group.h

+#ifndef _FILTERING_TEST_GROUP_H_
+#define _FILTERING_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(filtering_tests);
+
+#endif /* _FILTERING_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/filtering_tests/filtering_tests.h

+#ifndef _FILTERING_TESTS_H_
+#define _FILTERING_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DECLARE_GROUP(biquad_tests);
+JTEST_DECLARE_GROUP(conv_tests);
+JTEST_DECLARE_GROUP(correlate_tests);
+JTEST_DECLARE_GROUP(fir_tests);
+JTEST_DECLARE_GROUP(iir_tests);
+JTEST_DECLARE_GROUP(lms_tests);
+
+#endif /* _FILTERING_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_templates.h

+#ifndef _INTRINSICS_TEMPLATES_H_
+#define _INTRINSICS_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h>             /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+* Comparison SNR thresholds for the data types used in transform_tests.
+*/
+#define INTRINSICS_SNR_THRESHOLD_q63_t     120
+#define INTRINSICS_SNR_THRESHOLD_q31_t     95
+
+/**
+*  Compare the outputs from the function under test and the reference
+*  function using SNR.
+*/
+#define INTRINSICS_SNR_COMPARE_INTERFACE(block_size,  \
+   output_type)                                       \
+   do                                                 \
+   {                                                  \
+      TEST_CONVERT_AND_ASSERT_SNR(                    \
+         intrinsics_output_f32_ref,                   \
+         (output_type##_t *) intrinsics_output_ref,   \
+         intrinsics_output_f32_fut,                   \
+         (output_type##_t *) intrinsics_output_fut,   \
+         block_size,                                  \
+         output_type,                                 \
+         INTRINSICS_SNR_THRESHOLD_##output_type##_t   \
+      );                                              \
+   } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#define INTRINSICS_TEST_TEMPLATE_ELT1(functionName, dataType)              \
+                                                                           \
+   JTEST_DEFINE_TEST(functionName##_test, functionName)                    \
+   {                                                                       \
+      uint32_t i;                                                          \
+                                                                           \
+      JTEST_COUNT_CYCLES(                                                  \
+         for(i=0;i<INTRINSICS_MAX_LEN;i++)                                 \
+         {                                                                 \
+            *((dataType##_t*)intrinsics_output_fut + i) =                  \
+               functionName(                                               \
+                  (dataType##_t)intrinsics_##dataType##_inputs[i]);        \
+         });                                                               \
+                                                                           \
+      for(i=0;i<INTRINSICS_MAX_LEN;i++)                                    \
+      {                                                                    \
+         *((dataType##_t*)intrinsics_output_ref + i) =                     \
+            ref##functionName(                                             \
+               (dataType##_t)intrinsics_##dataType##_inputs[i]);           \
+      }                                                                    \
+                                                                           \
+      INTRINSICS_SNR_COMPARE_INTERFACE(                                    \
+         INTRINSICS_MAX_LEN,                                               \
+         dataType);                                                        \
+                                                                           \
+      return JTEST_TEST_PASSED;                                            \
+   }
+
+#define INTRINSICS_TEST_TEMPLATE_ELT2(functionName, dataType)              \
+                                                                           \
+   JTEST_DEFINE_TEST(functionName##_test, functionName)                    \
+   {                                                                       \
+      uint32_t i;                                                          \
+                                                                           \
+      JTEST_COUNT_CYCLES(                                                  \
+         for(i=0;i<INTRINSICS_MAX_LEN;i++)                                 \
+         {                                                                 \
+            *((dataType##_t*)intrinsics_output_fut + i) =                  \
+               functionName(                                               \
+                  (dataType##_t)intrinsics_##dataType##_inputs[i]          \
+                  ,(dataType##_t)intrinsics_##dataType##_inputs[i]);       \
+         });                                                               \
+                                                                           \
+      for(i=0;i<INTRINSICS_MAX_LEN;i++)                                    \
+      {                                                                    \
+         *((dataType##_t*)intrinsics_output_ref + i) =                     \
+            ref##functionName(                                             \
+               (dataType##_t)intrinsics_##dataType##_inputs[i]             \
+               ,(dataType##_t)intrinsics_##dataType##_inputs[i]);          \
+      }                                                                    \
+                                                                           \
+      INTRINSICS_SNR_COMPARE_INTERFACE(                                    \
+         INTRINSICS_MAX_LEN,                                               \
+         dataType);                                                        \
+                                                                           \
+      return JTEST_TEST_PASSED;                                            \
+   }
+
+#define INTRINSICS_TEST_TEMPLATE_ELT3(functionName, dataType)              \
+                                                                           \
+   JTEST_DEFINE_TEST(functionName##_test, functionName)                    \
+   {                                                                       \
+      uint32_t i;                                                          \
+                                                                           \
+      JTEST_COUNT_CYCLES(                                                  \
+         for(i=0;i<INTRINSICS_MAX_LEN;i++)                                 \
+         {                                                                 \
+            *((dataType##_t*)intrinsics_output_fut + i) =                  \
+               functionName(                                               \
+                  (dataType##_t)intrinsics_##dataType##_inputs[i]          \
+                  ,(dataType##_t)intrinsics_##dataType##_inputs[i]         \
+                  ,(dataType##_t)intrinsics_##dataType##_inputs[i]);       \
+         });                                                               \
+                                                                           \
+      for(i=0;i<INTRINSICS_MAX_LEN;i++)                                    \
+      {                                                                    \
+         *((dataType##_t*)intrinsics_output_ref + i) =                     \
+            ref##functionName(                                             \
+               (dataType##_t)intrinsics_##dataType##_inputs[i]             \
+               ,(dataType##_t)intrinsics_##dataType##_inputs[i]            \
+               ,(dataType##_t)intrinsics_##dataType##_inputs[i]);          \
+      }                                                                    \
+                                                                           \
+      INTRINSICS_SNR_COMPARE_INTERFACE(                                    \
+         INTRINSICS_MAX_LEN,                                               \
+         dataType);                                                        \
+                                                                           \
+      return JTEST_TEST_PASSED;                                            \
+   }
+
+#define INTRINSICS_TEST_TEMPLATE_ELT4(functionName, dataType, dataType2)   \
+   JTEST_DEFINE_TEST(functionName##_test, functionName)                    \
+   {                                                                       \
+      uint32_t i;                                                          \
+                                                                           \
+      JTEST_COUNT_CYCLES(                                                  \
+         for(i=0;i<INTRINSICS_MAX_LEN;i++)                                 \
+         {                                                                 \
+            *((dataType2##_t*)intrinsics_output_fut + i) =                 \
+               functionName(                                               \
+                  (dataType##_t)intrinsics_##dataType##_inputs[i]          \
+                  ,(dataType##_t)intrinsics_##dataType##_inputs[i]         \
+                  ,(dataType2##_t)intrinsics_##dataType2##_inputs[i]);     \
+         });                                                               \
+                                                                           \
+      for(i=0;i<INTRINSICS_MAX_LEN;i++)                                    \
+      {                                                                    \
+         *((dataType2##_t*)intrinsics_output_ref + i) =                    \
+            ref##functionName(                                             \
+               (dataType##_t)intrinsics_##dataType##_inputs[i]             \
+               ,(dataType##_t)intrinsics_##dataType##_inputs[i]            \
+               ,(dataType2##_t)intrinsics_##dataType2##_inputs[i]);        \
+      }                                                                    \
+                                                                           \
+      INTRINSICS_SNR_COMPARE_INTERFACE(                                    \
+         INTRINSICS_MAX_LEN,                                               \
+         dataType2);                                                       \
+                                                                           \
+      return JTEST_TEST_PASSED;                                            \
+   }
+
+#endif /* _INTRINSICS_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_data.h

+#ifndef _INTRINSICS_TEST_DATA_H_
+#define _INTRINSICS_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define INTRINSICS_MAX_LEN 1024
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+extern q63_t intrinsics_output_fut[INTRINSICS_MAX_LEN];
+extern q63_t intrinsics_output_ref[INTRINSICS_MAX_LEN];
+extern float32_t intrinsics_output_f32_fut[INTRINSICS_MAX_LEN];
+extern float32_t intrinsics_output_f32_ref[INTRINSICS_MAX_LEN];
+extern const q63_t intrinsics_q63_inputs[INTRINSICS_MAX_LEN];
+extern const q31_t *intrinsics_q31_inputs;
+
+#endif /* _INTRINSICS_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/intrinsics_tests/intrinsics_test_group.h

+#ifndef _INTRINSICS_TEST_GROUP_H_
+#define _INTRINSICS_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(intrinsics_tests);
+
+#endif /* _INTRINSICS_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/math_helper.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date:        29. November 2010
+* $Revision:    V1.0.3
+*
+* Project:      CMSIS DSP Library
+*
+* Title:        math_helper.h
+*
+*
+* Description:	Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.3 2010/11/29
+*    Re-organized the CMSIS folders and updated documentation.
+*
+* Version 1.0.2 2010/11/11
+*    Documentation updated.
+*
+* Version 1.0.1 2010/10/05
+*    Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20
+*    Production release and review comments incorporated.
+*
+* Version 0.0.7  2010/06/10
+*    Misra-C changes done
+* -------------------------------------------------------------------- */
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+#include "arm_math.h"
+
+float arm_snr_f32(float *pRef, float *pTest,  uint32_t buffSize);
+double arm_snr_f64(double *pRef, double *pTest,  uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_templates.h

+#ifndef _MATRIX_TEMPLATES_H_
+#define _MATRIX_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Compare the outputs from the function under test and the reference
+ *  function.
+ */
+#define MATRIX_COMPARE_INTERFACE(output_type, output_content_type)  \
+    TEST_ASSERT_BUFFERS_EQUAL(                                      \
+        ((output_type *) &matrix_output_ref)->pData,                \
+        ((output_type *) &matrix_output_fut)->pData,                \
+        ((output_type *) &matrix_output_fut)->numRows *             \
+        ((output_type *) &matrix_output_ref)->numCols *             \
+        sizeof(output_content_type))
+
+/**
+ * Comparison SNR thresholds for the data types used in matrix_tests.
+ */
+#define MATRIX_SNR_THRESHOLD 120
+
+/**
+ *  Compare the outputs from the function under test and the reference
+ *  function using SNR.
+ */
+#define MATRIX_SNR_COMPARE_INTERFACE(output_type, output_content_type)  \
+    do                                                                  \
+    {                                                                   \
+        TEST_CONVERT_AND_ASSERT_SNR(                                    \
+            (float32_t *)matrix_output_f32_ref,                         \
+            ((output_type *) &matrix_output_ref)->pData,                \
+            (float32_t *)matrix_output_f32_fut,                         \
+            ((output_type *) &matrix_output_ref)->pData,                \
+            ((output_type *) &matrix_output_fut)->numRows *             \
+            ((output_type *) &matrix_output_ref)->numCols,              \
+            output_content_type,                                        \
+            MATRIX_SNR_THRESHOLD                                        \
+            );                                                          \
+    } while (0)
+
+/**
+ *  Compare the outputs from the function under test and the reference
+ *  function using SNR. This is special for float64_t
+ */
+#define MATRIX_DBL_SNR_COMPARE_INTERFACE(output_type)                   \
+    do                                                                  \
+    {                                                                   \
+        TEST_ASSERT_DBL_SNR(                                            \
+            (float64_t *)matrix_output_f32_ref,                         \
+            (float64_t *)matrix_output_f32_fut,                         \
+            ((output_type *) &matrix_output_fut)->numRows *             \
+            ((output_type *) &matrix_output_ref)->numCols,              \
+            MATRIX_SNR_THRESHOLD                                        \
+            );                                                          \
+    } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define ARM_mat_add_INPUT_INTERFACE(input_a_ptr, input_b_ptr)    \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_add_INPUT_INTERFACE(input_a_ptr, input_b_ptr)    \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_cmplx_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr)    \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_cmplx_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr)    \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_inverse_INPUT_INTERFACE(input_ptr)  \
+    PAREN(input_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_inverse_INPUT_INTERFACE(input_ptr)  \
+    PAREN(input_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr)      \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_mult_INPUT_INTERFACE(input_a_ptr, input_b_ptr)      \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_mult_fast_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_mult_fast_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_sub_INPUT_INTERFACE(input_a_ptr, input_b_ptr)    \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_sub_INPUT_INTERFACE(input_a_ptr, input_b_ptr)    \
+    PAREN(input_a_ptr, input_b_ptr, (void *) &matrix_output_ref)
+
+#define ARM_mat_trans_INPUT_INTERFACE(input_ptr)    \
+    PAREN(input_ptr, (void *) &matrix_output_fut)
+
+#define REF_mat_trans_INPUT_INTERFACE(input_ptr)    \
+    PAREN(input_ptr, (void *) &matrix_output_ref)
+
+/*--------------------------------------------------------------------------------*/
+/* Dimension Validation Interfaces */
+/*--------------------------------------------------------------------------------*/
+
+#define MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS(input_type,   \
+                                              matrix_a_ptr, \
+                                              matrix_b_ptr) \
+    ((((input_type) (matrix_a_ptr))->numRows ==             \
+      ((input_type) (matrix_b_ptr))->numRows) &&            \
+     (((input_type) (matrix_a_ptr))->numCols ==             \
+      ((input_type) (matrix_b_ptr))->numCols))
+
+#define MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS(input_type,     \
+                                                    matrix_a_ptr,   \
+                                                    matrix_b_ptr)   \
+    (((input_type) (matrix_a_ptr))->numCols ==                      \
+     ((input_type) (matrix_b_ptr))->numRows)
+
+#define MATRIX_TEST_VALID_SQUARE_DIMENSIONS(input_type, \
+                                            matrix_ptr) \
+    (((input_type)(matrix_ptr))->numRows ==             \
+     ((input_type)(matrix_ptr))->numCols)
+
+#define MATRIX_TEST_VALID_DIMENSIONS_ALWAYS(input_type, \
+                                            matrix_ptr) \
+    (1 == 1)                                            \
+
+/*--------------------------------------------------------------------------------*/
+/* Output Configuration Interfaces */
+/*--------------------------------------------------------------------------------*/
+/* The matrix tests assume the output matrix is always the correct size.  These
+ * interfaces size the properly size the output matrices according to the input
+ * matrices and the operation at hand.*/
+
+#define MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT(input_type,      \
+                                           matrix_a_ptr,    \
+                                           matrix_b_ptr)    \
+    do                                                      \
+    {                                                       \
+        ((input_type) &matrix_output_fut)->numRows =        \
+            ((input_type)(matrix_a_ptr))->numRows;          \
+        ((input_type) &matrix_output_fut)->numCols =        \
+            ((input_type)(matrix_a_ptr))->numCols;          \
+        ((input_type) &matrix_output_ref)->numRows =        \
+            ((input_type)(matrix_a_ptr))->numRows;          \
+        ((input_type) &matrix_output_ref)->numCols =        \
+            ((input_type)(matrix_a_ptr))->numCols;          \
+    } while (0)
+
+#define MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT(input_type,    \
+                                                 matrix_a_ptr,  \
+                                                 matrix_b_ptr)  \
+    do                                                          \
+    {                                                           \
+        ((input_type) &matrix_output_fut)->numRows =            \
+            ((input_type)(matrix_a_ptr))->numRows;              \
+        ((input_type) &matrix_output_fut)->numCols =            \
+            ((input_type)(matrix_b_ptr))->numCols;              \
+        ((input_type) &matrix_output_ref)->numRows =            \
+            ((input_type)(matrix_a_ptr))->numRows;              \
+        ((input_type) &matrix_output_ref)->numCols =            \
+            ((input_type)(matrix_b_ptr))->numCols;              \
+    } while (0)
+
+#define MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(input_type,  \
+                                           matrix_ptr)  \
+    do                                                  \
+    {                                                   \
+        ((input_type) &matrix_output_fut)->numRows =    \
+            ((input_type)(matrix_ptr))->numRows;        \
+        ((input_type) &matrix_output_fut)->numCols =    \
+            ((input_type)(matrix_ptr))->numCols;        \
+        ((input_type) &matrix_output_ref)->numRows =    \
+            ((input_type)(matrix_ptr))->numRows;        \
+        ((input_type) &matrix_output_ref)->numCols =    \
+            ((input_type)(matrix_ptr))->numCols;        \
+    } while (0)
+
+#define MATRIX_TEST_CONFIG_TRANSPOSE_OUTPUT(input_type,     \
+                                            matrix_ptr)     \
+        do                                                  \
+        {                                                   \
+            ((input_type) &matrix_output_fut)->numRows =    \
+                ((input_type)(matrix_ptr))->numCols;        \
+            ((input_type) &matrix_output_fut)->numCols =    \
+                ((input_type)(matrix_ptr))->numRows;        \
+            ((input_type) &matrix_output_ref)->numRows =    \
+                ((input_type)(matrix_ptr))->numCols;        \
+            ((input_type) &matrix_output_ref)->numCols =    \
+                ((input_type)(matrix_ptr))->numRows;        \
+        } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#define MATRIX_TEST_TEMPLATE_ELT1(arr_desc_inputs,                      \
+                                  input_type,                           \
+                                  output_type, output_content_type,     \
+                                  fut, fut_arg_interface,               \
+                                  ref, ref_arg_interface,               \
+                                  output_config_interface,              \
+                                  dim_validation_interface,             \
+                                  compare_interface)                    \
+    do                                                                  \
+    {                                                                   \
+        TEMPLATE_DO_ARR_DESC(                                           \
+            input_idx, input_type, input, arr_desc_inputs               \
+            ,                                                           \
+            JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n",               \
+                         (int)input->numRows,                           \
+                         (int)input->numCols);                          \
+                                                                        \
+            if (dim_validation_interface(input_type,                     \
+                                        input)) {                       \
+                output_config_interface(input_type,                     \
+                                        input);                         \
+                TEST_CALL_FUT_AND_REF(                                  \
+                    fut, fut_arg_interface(input),                      \
+                    ref, ref_arg_interface(input));                     \
+                compare_interface(output_type,                          \
+                                  output_content_type);                 \
+            } else {                                                    \
+                arm_status matrix_test_retval;                          \
+                TEST_CALL_FUT(                                          \
+                    matrix_test_retval = fut,                           \
+                    fut_arg_interface(input));                          \
+                                                                        \
+                /* If dimensions are known bad, the fut should */       \
+                /* detect it. */                                        \
+                if ( matrix_test_retval != ARM_MATH_SIZE_MISMATCH) {     \
+                    return JTEST_TEST_FAILED;                           \
+                }                                                       \
+            });                                                         \
+        return JTEST_TEST_PASSED;                                       \
+    } while (0)
+
+
+#define MATRIX_TEST_TEMPLATE_ELT2(arr_desc_inputs_a,                    \
+                                  arr_desc_inputs_b,                    \
+                                  input_type,                           \
+                                  output_type, output_content_type,     \
+                                  fut, fut_arg_interface,               \
+                                  ref, ref_arg_interface,               \
+                                  output_config_interface,              \
+                                  dim_validation_interface,             \
+                                  compare_interface)                    \
+    do                                                                  \
+    {                                                                   \
+        TEMPLATE_DO_ARR_DESC(                                           \
+            input_a_idx, input_type, input_a, arr_desc_inputs_a         \
+            ,                                                           \
+            input_type input_b = ARR_DESC_ELT(                          \
+                input_type, input_a_idx,                                \
+                &(arr_desc_inputs_b));                                  \
+                                                                        \
+            JTEST_DUMP_STRF("Matrix Dimensions: A %dx%d  B %dx%d\n",    \
+                     (int)input_a->numRows,                             \
+                     (int)input_a->numCols,                             \
+                     (int)input_b->numRows,                             \
+                     (int)input_b->numCols);                            \
+                                                                        \
+            if (dim_validation_interface(input_type,                     \
+                                        input_a,                        \
+                                        input_b)) {                     \
+                                                                        \
+                output_config_interface(input_type,                     \
+                                        input_a,                        \
+                                        input_b);                       \
+                                                                        \
+                TEST_CALL_FUT_AND_REF(                                  \
+                    fut, fut_arg_interface(input_a, input_b),           \
+                    ref, ref_arg_interface(input_a, input_b));          \
+                                                                        \
+                compare_interface(output_type, output_content_type);    \
+                                                                        \
+            } else {                                                    \
+                arm_status matrix_test_retval;                          \
+                TEST_CALL_FUT(                                          \
+                    matrix_test_retval = fut, fut_arg_interface(input_a, input_b)); \
+                                                                        \
+                /* If dimensions are known bad, the fut should */       \
+                /* detect it. */                                        \
+                if ( matrix_test_retval != ARM_MATH_SIZE_MISMATCH) {     \
+                    return JTEST_TEST_FAILED;                           \
+                }                                                       \
+            });                                                         \
+        return JTEST_TEST_PASSED;                                       \
+    } while (0)
+
+/**
+ *  Specialization of #MATRIX_TEST_TEMPLATE_ELT2() for matrix tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define MATRIX_DEFINE_TEST_TEMPLATE_ELT2(fn_name, suffix,           \
+                                         output_config_interface,   \
+                                         dim_validation_interface,  \
+                                         comparison_interface)      \
+        JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,          \
+                          arm_##fn_name##_##suffix)                 \
+        {                                                           \
+            MATRIX_TEST_TEMPLATE_ELT2(                              \
+                matrix_##suffix##_a_inputs,                         \
+                matrix_##suffix##_b_inputs,                         \
+                arm_matrix_instance_##suffix * ,                    \
+                arm_matrix_instance_##suffix,                       \
+                TYPE_FROM_ABBREV(suffix),                           \
+                arm_##fn_name##_##suffix,                           \
+                ARM_##fn_name##_INPUT_INTERFACE,                    \
+                ref_##fn_name##_##suffix,                           \
+                REF_##fn_name##_INPUT_INTERFACE,                    \
+                output_config_interface,                            \
+                dim_validation_interface,                           \
+                comparison_interface);                              \
+        }                                                           \
+
+/**
+ *  Specialization of #MATRIX_TEST_TEMPLATE_ELT1() for matrix tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define MATRIX_DEFINE_TEST_TEMPLATE_ELT1(fn_name, suffix,           \
+                                         output_config_interface,   \
+                                         dim_validation_interface)  \
+        JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,          \
+                          arm_##fn_name##_##suffix)                 \
+        {                                                           \
+            MATRIX_TEST_TEMPLATE_ELT1(                              \
+                matrix_##suffix##_a_inputs,                         \
+                arm_matrix_instance_##suffix * ,                    \
+                arm_matrix_instance_##suffix,                       \
+                TYPE_FROM_ABBREV(suffix),                           \
+                arm_##fn_name##_##suffix,                           \
+                ARM_##fn_name##_INPUT_INTERFACE,                    \
+                ref_##fn_name##_##suffix,                           \
+                REF_##fn_name##_INPUT_INTERFACE,                    \
+                output_config_interface,                            \
+                dim_validation_interface,                           \
+                MATRIX_COMPARE_INTERFACE);                          \
+        }                                                           \
+
+
+#endif /* _MATRIX_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_data.h

+#ifndef _MATRIX_TEST_DATA_H_
+#define _MATRIX_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"           /* float32_t */
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define MATRIX_TEST_MAX_ROWS 4
+#define MATRIX_TEST_MAX_COLS 4
+#define MATRIX_TEST_BIGGEST_INPUT_TYPE float64_t
+#define MATRIX_TEST_MAX_ELTS (MATRIX_TEST_MAX_ROWS * MATRIX_TEST_MAX_COLS)
+#define MATRIX_MAX_COEFFS_LEN 16
+#define MATRIX_MAX_SHIFTS_LEN 5
+
+/**
+ *  Declare the matrix inputs defined by MATRIX_DEFINE_INPUTS.
+ */
+#define MATRIX_DECLARE_INPUTS(suffix)               \
+    ARR_DESC_DECLARE(matrix_##suffix##_a_inputs);   \
+    ARR_DESC_DECLARE(matrix_##suffix##_b_inputs);   \
+    ARR_DESC_DECLARE(matrix_##suffix##_invertible_inputs)
+
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+extern arm_matrix_instance_f32 matrix_output_fut;
+extern arm_matrix_instance_f32 matrix_output_ref;
+extern arm_matrix_instance_f64 matrix_output_fut64;
+extern arm_matrix_instance_f64 matrix_output_ref64;
+extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_fut[MATRIX_TEST_MAX_ELTS];
+extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_ref[MATRIX_TEST_MAX_ELTS];
+extern MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_scratch[MATRIX_TEST_MAX_ELTS];
+
+/* Matrix Inputs */
+MATRIX_DECLARE_INPUTS(f64);
+MATRIX_DECLARE_INPUTS(f32);
+MATRIX_DECLARE_INPUTS(q31);
+MATRIX_DECLARE_INPUTS(q15);
+
+extern const float32_t matrix_f32_scale_values[MATRIX_MAX_COEFFS_LEN];
+extern const q31_t matrix_q31_scale_values[MATRIX_MAX_COEFFS_LEN];
+extern const q15_t matrix_q15_scale_values[MATRIX_MAX_COEFFS_LEN];
+extern const int32_t matrix_shift_values[MATRIX_MAX_SHIFTS_LEN];
+
+#endif /* _MATRIX_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h

+#ifndef _MATRIX_TEST_GROUP_H_
+#define _MATRIX_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(matrix_tests);
+
+#endif /* _MATRIX_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h

+#ifndef _MATRIX_TESTS_H_
+#define _MATRIX_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(mat_add_tests);
+JTEST_DECLARE_GROUP(mat_cmplx_mult_tests);
+JTEST_DECLARE_GROUP(mat_init_tests);
+JTEST_DECLARE_GROUP(mat_inverse_tests);
+JTEST_DECLARE_GROUP(mat_mult_tests);
+JTEST_DECLARE_GROUP(mat_mult_fast_tests);
+JTEST_DECLARE_GROUP(mat_sub_tests);
+JTEST_DECLARE_GROUP(mat_trans_tests);
+JTEST_DECLARE_GROUP(mat_scale_tests);
+
+#endif /* _MATRIX_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h

+#ifndef _STATISTICS_TEMPLATES_H_
+#define _STATISTICS_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Compare the outputs from the function under test and the reference function.
+ */
+#define STATISTICS_COMPARE_INTERFACE(block_size,    \
+                                     output_type)   \
+    do                                              \
+    {                                               \
+        TEST_ASSERT_BUFFERS_EQUAL(                  \
+            statistics_output_ref.data_ptr,         \
+            statistics_output_fut.data_ptr,         \
+            1 * sizeof(output_type) /* All fns return one value*/   \
+            );                                      \
+        TEST_ASSERT_EQUAL(                          \
+            statistics_idx_fut,                     \
+            statistics_idx_ref);                    \
+    } while (0)                                      \
+
+/*
+ * Comparison SNR thresholds for the data types used in statistics_tests.
+ */
+#define STATISTICS_SNR_THRESHOLD_float32_t 120
+#define STATISTICS_SNR_THRESHOLD_q31_t 100
+#define STATISTICS_SNR_THRESHOLD_q15_t 60
+#define STATISTICS_SNR_THRESHOLD_q7_t 30
+
+/**
+ *  Compare reference and fut outputs using SNR.
+ *
+ *  @note The outputs are converted to float32_t before comparison.
+ */
+#define STATISTICS_SNR_COMPARE_INTERFACE(block_size,    \
+                                         output_type)   \
+    do                                                  \
+    {                                                   \
+        TEST_CONVERT_AND_ASSERT_SNR(                    \
+            statistics_output_f32_ref,                  \
+            statistics_output_ref.data_ptr,             \
+            statistics_output_f32_fut,                  \
+            statistics_output_fut.data_ptr,             \
+                1, /* All fns return one element*/      \
+            output_type,                                \
+            STATISTICS_SNR_THRESHOLD_##output_type      \
+            );                                          \
+    } while (0)
+
+
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define ARM_max_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size,                                    \
+          statistics_output_fut.data_ptr, &statistics_idx_fut)
+
+#define REF_max_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size,                                    \
+          statistics_output_ref.data_ptr, &statistics_idx_ref)
+
+#define ARM_mean_INPUT_INTERFACE(input, block_size)             \
+    PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_mean_INPUT_INTERFACE(input, block_size)             \
+    PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+#define ARM_min_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size,                                    \
+          statistics_output_fut.data_ptr, &statistics_idx_fut)
+
+#define REF_min_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size,                                    \
+          statistics_output_ref.data_ptr, &statistics_idx_ref)
+
+#define ARM_power_INPUT_INTERFACE(input, block_size)            \
+    PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_power_INPUT_INTERFACE(input, block_size)            \
+    PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+#define ARM_rms_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_rms_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+#define ARM_std_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_std_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+#define ARM_var_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size, statistics_output_fut.data_ptr)
+
+#define REF_var_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, block_size, statistics_output_ref.data_ptr)
+
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_BLK() for statistics tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name,       \
+                                                 suffix,        \
+                                                 input_type,    \
+                                                 output_type,   \
+                                                 comparison_interface)  \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,          \
+                      arm_##fn_name##_##suffix)                 \
+    {                                                           \
+        TEST_TEMPLATE_BUF1_BLK(                                 \
+            statistics_f_all,                                   \
+            statistics_block_sizes,                             \
+            input_type,                                         \
+            output_type,                                        \
+            arm_##fn_name##_##suffix,                           \
+            ARM_##fn_name##_INPUT_INTERFACE,                    \
+            ref_##fn_name##_##suffix,                           \
+            REF_##fn_name##_INPUT_INTERFACE,                    \
+            comparison_interface);                              \
+    }
+
+
+#endif /* _STATISTICS_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h

+#ifndef _STATISTICS_TEST_DATA_H_
+#define _STATISTICS_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define STATISTICS_MAX_INPUT_ELEMENTS 32
+#define STATISTICS_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(statistics_output_fut);
+ARR_DESC_DECLARE(statistics_output_ref);
+extern uint32_t statistics_idx_fut;
+extern uint32_t statistics_idx_ref;
+
+extern STATISTICS_BIGGEST_INPUT_TYPE
+statistics_output_f32_ref[STATISTICS_MAX_INPUT_ELEMENTS];
+
+extern STATISTICS_BIGGEST_INPUT_TYPE
+statistics_output_f32_fut[STATISTICS_MAX_INPUT_ELEMENTS];
+
+
+/* Block Sizes */
+ARR_DESC_DECLARE(statistics_block_sizes);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(statistics_zeros);
+ARR_DESC_DECLARE(statistics_f_2);
+ARR_DESC_DECLARE(statistics_f_15);
+ARR_DESC_DECLARE(statistics_f_32);
+ARR_DESC_DECLARE(statistics_f_all);
+
+#endif /* _STATISTICS_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_group.h

+#ifndef _STATISTICS_TEST_GROUP_H_
+#define _STATISTICS_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(statistics_tests);
+
+#endif /* _STATISTICS_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_tests.h

+#ifndef _STATISTICS_TESTS_H_
+#define _STATISTICS_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(max_tests);
+JTEST_DECLARE_GROUP(mean_tests);
+JTEST_DECLARE_GROUP(min_tests);
+JTEST_DECLARE_GROUP(power_tests);
+JTEST_DECLARE_GROUP(rms_tests);
+JTEST_DECLARE_GROUP(std_tests);
+JTEST_DECLARE_GROUP(var_tests);
+
+#endif /* _STATISTICS_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_templates.h

+#ifndef _SUPPORT_TEMPLATES_H_
+#define _SUPPORT_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Compare the outputs from the function under test and the reference function.
+ */
+#define SUPPORT_COMPARE_INTERFACE(block_size,   \
+                                  output_type)  \
+    do                                          \
+    {                                           \
+        TEST_ASSERT_BUFFERS_EQUAL(              \
+            support_output_ref.data_ptr,        \
+            support_output_fut.data_ptr,        \
+            block_size * sizeof(output_type));  \
+    } while (0)                                  \
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define ARM_copy_INPUT_INTERFACE(input, block_size)         \
+    PAREN(input, support_output_fut.data_ptr, block_size)
+
+#define REF_copy_INPUT_INTERFACE(input, block_size)         \
+    PAREN(input, support_output_ref.data_ptr, block_size)
+
+#define ARM_fill_INPUT_INTERFACE(elt, block_size)       \
+    PAREN(elt, support_output_fut.data_ptr, block_size)
+
+#define REF_fill_INPUT_INTERFACE(elt, block_size)       \
+    PAREN(elt, support_output_ref.data_ptr, block_size)
+
+#define ARM_x_to_y_INPUT_INTERFACE(input, block_size)       \
+    PAREN(input, support_output_fut.data_ptr, block_size)
+
+#define REF_x_to_y_INPUT_INTERFACE(input, block_size)       \
+    PAREN(input, support_output_ref.data_ptr, block_size)
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_BLK() for support tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define SUPPORT_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name,              \
+                                              suffix,               \
+                                              input_type,           \
+                                              output_type,          \
+                                              comparison_interface) \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF1_BLK(                                     \
+            support_f_all,                                          \
+            support_block_sizes,                                    \
+            input_type,                                             \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            comparison_interface);                                  \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_ELT1_BLK() for support tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define SUPPORT_DEFINE_TEST_TEMPLATE_ELT1_BLK(fn_name,              \
+                                              suffix,               \
+                                              elt_type,             \
+                                              output_type,          \
+                                              comparison_interface) \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_ELT1_BLK(                                     \
+            support_elts,                                           \
+            support_block_sizes,                                    \
+            elt_type,                                               \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            comparison_interface);                                  \
+    }
+
+#endif /* _SUPPORT_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_data.h

+#ifndef ARM_SUPPORT_TEST_DATA_H
+#define ARM_SUPPORT_TEST_DATA_H
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(support_output_fut);
+ARR_DESC_DECLARE(support_output_ref);
+
+/* Block Sizes*/
+ARR_DESC_DECLARE(support_block_sizes);
+
+/* Numbers */
+ARR_DESC_DECLARE(support_elts);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(support_zeros);
+ARR_DESC_DECLARE(support_f_2);
+ARR_DESC_DECLARE(support_f_15);
+ARR_DESC_DECLARE(support_f_32);
+ARR_DESC_DECLARE(support_f_all);
+
+#endif

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_test_group.h

+#ifndef _SUPPORT_TEST_GROUP_H_
+#define _SUPPORT_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(support_tests);
+
+#endif /* _SUPPORT_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/support_tests/support_tests.h

+#ifndef _SUPPORT_TESTS_H_
+#define _SUPPORT_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(copy_tests);
+JTEST_DECLARE_GROUP(fill_tests);
+JTEST_DECLARE_GROUP(x_to_y_tests);
+
+#endif /* _SUPPORT_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/template.h

+#ifndef _TEMPLATE_H_
+#define _TEMPLATE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Looping and Iteration */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Template for the general structure of a loop.
+ */
+#define TEMPLATE_LOOP(setup, loop_def, body)    \
+    do                                          \
+    {                                           \
+        setup;                                  \
+        loop_def {                              \
+            body;                               \
+        }                                       \
+    } while (0)
+
+/**
+ *  Template for looping over an array-like sequence.
+ */
+#define TEMPLATE_DO_ARR_LIKE(iter_idx, type,                            \
+                             arr, arr_length,                           \
+                             iter_elem_setup,                           \
+                             body)                                      \
+    do                                                                  \
+    {                                                                   \
+        TEMPLATE_LOOP(                                                  \
+            int iter_idx,                                               \
+            for(iter_idx = 0; iter_idx < (arr_length); ++iter_idx),     \
+            iter_elem_setup;                                            \
+            body);                                                      \
+    } while (0)
+
+/**
+ *  Template for looping over the contents of an array.
+ */
+#define TEMPLATE_DO_ARR(iter_idx, type, iter_elem, arr, arr_length, body) \
+    do                                                                  \
+    {                                                                   \
+        TEMPLATE_DO_ARR_LIKE(                                           \
+            iter_idx, type, arr, arr_length,                            \
+            type iter_elem = (arr)[iter_idx],                           \
+            body);                                                      \
+    } while (0)
+
+/**
+ *  Template for looping over the contents of an #ARR_DESC.
+ */
+#define TEMPLATE_DO_ARR_DESC(iter_idx, type, iter_elem, arr_desc, body) \
+    do                                                                  \
+    {                                                                   \
+        TEMPLATE_DO_ARR_LIKE(                                           \
+            iter_idx, type, arr_desc, (arr_desc).element_count,         \
+            type iter_elem = ARR_DESC_ELT(type, iter_idx, &(arr_desc)), \
+            body);                                                      \
+    } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Test Definition */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Template for the general structure of a test.
+ */
+#define TEMPLATE_TEST(setup, body, teardown)    \
+        do                                      \
+        {                                       \
+            setup;                              \
+            body;                               \
+            teardown;                           \
+        } while (0)
+
+/**
+ *  Template for calling a function.
+ *
+ *  @note Surround function arguments with the #PAREN() macro.
+ *
+ *  @example
+ *  void my_func(int arg1, int arg2);
+ *
+ *  TEMPLATE_CALL_FN(my_func, PAREN(3, 7));
+ */
+#define TEMPLATE_CALL_FN(fn, fn_args)           \
+        fn fn_args
+
+#endif /* _TEMPLATE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h

+#ifndef _TEST_TEMPLATES_H_
+#define _TEST_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "template.h"
+#include <string.h>             /* memcmp() */
+#include <inttypes.h>           /* PRIu32 */
+#include "math_helper.h"        /* arm_snr_f32() */
+
+/*--------------------------------------------------------------------------------*/
+/* Function Aliases for use in Templates. */
+/*--------------------------------------------------------------------------------*/
+#define ref_q31_t_to_float ref_q31_to_float
+#define ref_q15_t_to_float ref_q15_to_float
+#define ref_q7_t_to_float  ref_q7_to_float
+#define ref_float_to_q31_t ref_float_to_q31
+#define ref_float_to_q15_t ref_float_to_q15
+#define ref_float_to_q7_t  ref_float_to_q7
+#define ref_float32_t_to_float ref_copy_f32
+#define ref_float_to_float32_t ref_copy_f32
+
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Call the function-under-test.
+ */
+#define TEST_CALL_FUT(fut, fut_args)                    \
+    JTEST_COUNT_CYCLES(TEMPLATE_CALL_FN(fut, fut_args))
+
+/**
+ *  Call the reference-function.
+ */
+#define TEST_CALL_REF(ref, ref_args)            \
+    TEMPLATE_CALL_FN(ref, ref_args)
+
+/**
+ *  Call the function-under-test and the reference-function.
+ */
+#define TEST_CALL_FUT_AND_REF(fut, fut_args, ref, ref_args) \
+    do {                                                    \
+        TEST_CALL_FUT(fut, fut_args);                       \
+        TEST_CALL_REF(ref, ref_args);                       \
+    } while (0)
+
+/**
+ *  This macro eats a variable number of arguments and evaluates to a null
+ *  statement.
+ */
+#define TEST_NULL_STATEMENT(...) (void) "TEST_NULL_STATEMENT"
+
+/**
+ *  A function name, Usable in any template where a fut or ref name is accepted,
+ *  that evaluates to a #TEST_NULL_STATEMENT().
+ */
+#define TEST_NULL_FN TEST_NULL_STATEMENT
+
+/**
+ *  Assert that buffers A and B are byte-equivalent for a number of bytes.
+ */
+#define TEST_ASSERT_BUFFERS_EQUAL(buf_a, buf_b, bytes)  \
+    do                                                  \
+    {                                                   \
+        if (memcmp(buf_a, buf_b, bytes) != 0)           \
+        {                                               \
+            return JTEST_TEST_FAILED;                   \
+        }                                               \
+    } while (0)
+
+/**
+ *  Assert that the two entities are equal.
+ */
+#define TEST_ASSERT_EQUAL(a, b)                         \
+    do                                                  \
+    {                                                   \
+        if ((a) != (b))                                 \
+        {                                               \
+            return JTEST_TEST_FAILED;                   \
+        }                                               \
+    } while (0)
+
+/**
+ *  Convert elements to from src_type to float.
+ */
+#define TEST_CONVERT_TO_FLOAT(src_ptr, dst_ptr, block_size, src_type)   \
+    do                                                                  \
+    {                                                                   \
+        ref_##src_type##_to_float(                                      \
+            src_ptr,                                                    \
+            dst_ptr,                                                    \
+            block_size);                                                \
+        } while (0)                                                      \
+
+/**
+ *  Convert elements to from float to dst_type .
+ */
+#define TEST_CONVERT_FLOAT_TO(src_ptr, dst_ptr, block_size, dst_type)   \
+    do                                                                  \
+    {                                                                   \
+        ref_float_to_##dst_type(                                        \
+            src_ptr,                                                    \
+            dst_ptr,                                                    \
+            block_size);                                                \
+    } while (0)                                                          \
+
+/**
+ *  Assert that the SNR between a reference and test sample is above a given
+ *  threshold.
+ */
+#define TEST_ASSERT_SNR(ref_ptr, tst_ptr, block_size, threshold)    \
+    do                                                              \
+    {                                                               \
+        float32_t snr = arm_snr_f32(ref_ptr, tst_ptr, block_size);  \
+        if ( snr <= threshold)                                       \
+        {                                                           \
+            JTEST_DUMP_STRF("SNR: %f\n", snr);                      \
+            return JTEST_TEST_FAILED;                               \
+        }                                                           \
+    } while (0)                                                      \
+
+/**
+ *  Assert that the SNR between a reference and test sample is above a given
+ *  threshold.  Special case for float64_t
+ */
+#define TEST_ASSERT_DBL_SNR(ref_ptr, tst_ptr, block_size, threshold)    \
+    do                                                              \
+    {                                                               \
+        float64_t snr = arm_snr_f64(ref_ptr, tst_ptr, block_size);  \
+        if ( snr <= threshold)                                       \
+        {                                                           \
+            JTEST_DUMP_STRF("SNR: %f\n", snr);                      \
+            return JTEST_TEST_FAILED;                               \
+        }                                                           \
+    } while (0)                                                      \
+
+/**
+ *  Compare test and reference elements by converting to float and
+ *  calculating an SNR.
+ *
+ *  This macro is a merger of the #TEST_CONVERT_TO_FLOAT() and
+ *  #TEST_ASSERT_SNR() macros.
+ */
+#define TEST_CONVERT_AND_ASSERT_SNR(ref_dst_ptr, ref_src_ptr,   \
+                                    tst_dst_ptr, tst_src_ptr,   \
+                                    block_size,                 \
+                                    tst_src_type,               \
+                                    threshold)                  \
+        do                                                      \
+        {                                                       \
+            TEST_CONVERT_TO_FLOAT(ref_src_ptr,                  \
+                                  ref_dst_ptr,                  \
+                                  block_size,                   \
+                                  tst_src_type);                \
+            TEST_CONVERT_TO_FLOAT(tst_src_ptr,                  \
+                                  tst_dst_ptr,                  \
+                                  block_size,                   \
+                                  tst_src_type);                \
+            TEST_ASSERT_SNR(ref_dst_ptr,                        \
+                            tst_dst_ptr,                        \
+                            block_size,                         \
+                            threshold);                         \
+        } while (0)
+
+/**
+ *  Execute statements only if the combination of block size, function type
+ *  specifier, and input ARR_DESC_t are valid.
+ *
+ *  @example An ARR_DESC_t that contains 64 bytes cant service a 32 element
+ *  block size if they are extracted in float32_t increments.
+ *
+ *  8 * 32 = 256 > 64.
+ */
+#define TEST_DO_VALID_BLOCKSIZE(block_size, fn_type_spec,   \
+                                input_arr_desc, body)       \
+    do                                                      \
+    {                                                       \
+        if (block_size * sizeof(fn_type_spec) <=             \
+           ARR_DESC_BYTES(input_arr_desc))                  \
+        {                                                   \
+            JTEST_DUMP_STRF("Block Size: %"PRIu32"\n", block_size); \
+            body;                                           \
+        }                                                   \
+    } while (0)                                              \
+
+/**
+ *  Template for tests that rely on one input buffer and a blocksize parameter.
+ *
+ *  The buffer is an #ARR_DESC_t.  It is iterated over and it's values are
+ *  passed to the function under test and reference functions through their
+ *  appropriate argument interfaces.  The argument interfaces this template to
+ *  execute structurally similar functions.
+ *
+ */
+#define TEST_TEMPLATE_BUF1_BLK(arr_desc_inputs,                         \
+                              arr_desc_block_sizes,                     \
+                              input_type, output_type,                  \
+                              fut, fut_arg_interface,                   \
+                              ref, ref_arg_interface,                   \
+                              compare_interface)                        \
+    do                                                                  \
+    {                                                                   \
+        TEMPLATE_DO_ARR_DESC(                                           \
+            input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs         \
+            ,                                                           \
+            TEMPLATE_DO_ARR_DESC(                                       \
+                block_size_idx, uint32_t, block_size, arr_desc_block_sizes \
+                ,                                                       \
+                void *   input_data_ptr = input_ptr->data_ptr;          \
+                                                                        \
+                TEST_DO_VALID_BLOCKSIZE(                                \
+                    block_size, input_type, input_ptr                   \
+                    ,                                                   \
+                    TEST_CALL_FUT_AND_REF(                              \
+                        fut, fut_arg_interface(                         \
+                            input_data_ptr, block_size),                \
+                        ref, ref_arg_interface(                         \
+                            input_data_ptr, block_size));               \
+                                                                        \
+                    compare_interface(block_size, output_type))));      \
+                                                                        \
+        return JTEST_TEST_PASSED;                                       \
+                                                                        \
+    } while (0)
+
+/**
+ *  Template for tests that rely on an input buffer and an element.
+ *
+ *  An element can is any thing which doesn't walk and talk like a
+ *  sequence. Examples include numbers, and structures.
+ */
+#define TEST_TEMPLATE_BUF1_ELT1(arr_desc_inputs,                        \
+                                arr_desc_elts,                          \
+                                input_type, elt_type, output_type,      \
+                                fut, fut_arg_interface,                 \
+                                ref, ref_arg_interface,                 \
+                                compare_interface)                      \
+        do                                                              \
+        {                                                               \
+            TEMPLATE_DO_ARR_DESC(                                       \
+                input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs     \
+                ,                                                       \
+                TEMPLATE_DO_ARR_DESC(                                   \
+                    elt_idx, elt_type, elt, arr_desc_elts               \
+                    ,                                                   \
+                    void * input_data_ptr = input_ptr->data_ptr;        \
+                    TEST_CALL_FUT_AND_REF(                              \
+                        fut, fut_arg_interface(input_data_ptr, elt),    \
+                        ref, ref_arg_interface(input_data_ptr, elt));   \
+                                                                        \
+                    compare_interface(output_type)));                   \
+            return JTEST_TEST_PASSED;                                   \
+        } while (0)
+
+/**
+ *  Template for tests that rely on an input buffer, an element, and a blocksize
+ *  parameter.
+ */
+#define TEST_TEMPLATE_BUF1_ELT1_BLK(arr_desc_inputs,                \
+                                    arr_desc_elts,                  \
+                                    arr_desc_block_sizes,           \
+                                    input_type, elt_type, output_type,  \
+                                    fut, fut_arg_interface,         \
+                                    ref, ref_arg_interface,         \
+                                    compare_interface);             \
+    do                                                              \
+    {                                                               \
+        TEMPLATE_DO_ARR_DESC(                                       \
+            inut_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs      \
+            ,                                                       \
+            TEMPLATE_DO_ARR_DESC(                                   \
+                block_size_idx, uint32_t, block_size,               \
+                arr_desc_block_sizes                                \
+                ,                                                   \
+                TEMPLATE_DO_ARR_DESC(                               \
+                    elt_idx, elt_type, elt, arr_desc_elts           \
+                    ,                                               \
+                    void * input_data_ptr = input_ptr->data_ptr;    \
+                    TEST_DO_VALID_BLOCKSIZE(                        \
+                        block_size, input_type, input_ptr,          \
+                                              \
+                        TEST_CALL_FUT_AND_REF(                      \
+                            fut, fut_arg_interface(                 \
+                                input_data_ptr, elt, block_size),   \
+                            ref, ref_arg_interface(                 \
+                                input_data_ptr, elt, block_size));  \
+                        compare_interface(block_size, output_type))))); \
+        return JTEST_TEST_PASSED;                                   \
+    } while (0)
+
+/**
+ *  Template for tests that rely on an input buffer, two elements, and a blocksize
+ *  parameter.
+ */
+#define TEST_TEMPLATE_BUF1_ELT2_BLK(arr_desc_inputs,                    \
+                                    arr_desc_elt1s,                     \
+                                    arr_desc_elt2s,                     \
+                                    arr_desc_block_sizes,               \
+                                    input_type, elt1_type,              \
+                                    elt2_type, output_type,             \
+                                    fut, fut_arg_interface,             \
+                                    ref, ref_arg_interface,             \
+                                    compare_interface)                  \
+        do                                                              \
+        {                                                               \
+            TEMPLATE_DO_ARR_DESC(                                       \
+                inut_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs      \
+                ,                                                       \
+                TEMPLATE_DO_ARR_DESC(                                   \
+                    block_size_idx, uint32_t, block_size,               \
+                    arr_desc_block_sizes                                \
+                    ,                                                   \
+                    TEMPLATE_DO_ARR_DESC(                               \
+                        elt1_idx, elt1_type, elt1, arr_desc_elt1s       \
+                        ,                                               \
+                        TEMPLATE_DO_ARR_DESC(                           \
+                            elt2_idx, elt2_type, elt2, arr_desc_elt2s   \
+                            ,                                           \
+                            void * input_data_ptr = input_ptr->data_ptr; \
+                            TEST_DO_VALID_BLOCKSIZE(                    \
+                                block_size, input_type, input_ptr,      \
+                                TEST_CALL_FUT_AND_REF(                  \
+                                    fut, fut_arg_interface(             \
+                                        input_data_ptr, elt1, elt2, block_size), \
+                                    ref, ref_arg_interface(             \
+                                        input_data_ptr, elt1, elt2, block_size)); \
+                                compare_interface(block_size, output_type)))))); \
+            return JTEST_TEST_PASSED;                                   \
+        } while (0)
+
+/**
+ *  Template for tests that rely on two input buffers and a blocksize parameter.
+ *
+ *  The two #ARR_DESC_t, input buffers are iterated through in parallel. The
+ *  length of the first #ARR_DESC_t determines the length of the iteration.
+ */
+#define TEST_TEMPLATE_BUF2_BLK(arr_desc_inputs_a,                       \
+                              arr_desc_inputs_b,                        \
+                              arr_desc_block_sizes,                     \
+                              input_type, output_type,                  \
+                              fut, fut_arg_interface,                   \
+                              ref, ref_arg_interface,                   \
+                              compare_interface)                        \
+    do                                                                  \
+    {                                                                   \
+        /* Iterate over two input arrays in parallel.*/                 \
+        TEMPLATE_DO_ARR_DESC(                                           \
+            input_idx, ARR_DESC_t *, input_ptr, arr_desc_inputs_a       \
+            ,                                                           \
+            TEMPLATE_DO_ARR_DESC(                                       \
+                block_size_idx, uint32_t, block_size, arr_desc_block_sizes, \
+                void * input_a_ptr = input_ptr->data_ptr;               \
+                void * input_b_ptr = ARR_DESC_ELT(                      \
+                    ARR_DESC_t *, input_idx,                            \
+                    &(arr_desc_inputs_b))->data_ptr;                    \
+                                                                        \
+                TEST_DO_VALID_BLOCKSIZE(                                \
+                    block_size, input_type, input_ptr                   \
+                    ,                                                   \
+                    TEST_CALL_FUT_AND_REF(                              \
+                        fut, fut_arg_interface(                         \
+                            input_a_ptr, input_b_ptr, block_size),      \
+                        ref, ref_arg_interface(                         \
+                            input_a_ptr, input_b_ptr, block_size));     \
+                                                                        \
+                    compare_interface(block_size, output_type))));      \
+        return JTEST_TEST_PASSED;                                       \
+    } while (0)
+
+/**
+ *  Test template that uses a single element.
+ */
+#define TEST_TEMPLATE_ELT1(arr_desc_elts,                       \
+                           elt_type, output_type,               \
+                           fut, fut_arg_interface,              \
+                           ref, ref_arg_interface,              \
+                           compare_interface)                   \
+        do                                                      \
+        {                                                       \
+            TEMPLATE_DO_ARR_DESC(                               \
+                elt_idx, elt_type, elt, arr_desc_elts           \
+                ,                                               \
+                TEST_CALL_FUT_AND_REF(                          \
+                    fut, fut_arg_interface(                     \
+                        elt),                                   \
+                    ref, ref_arg_interface(                     \
+                        elt));                                  \
+                /* Comparison interfaces typically accept */    \
+                /* a block_size. Pass a dummy value 1.*/        \
+                compare_interface(1, output_type));             \
+            return JTEST_TEST_PASSED;                           \
+        } while (0)
+
+/**
+ *  Test template that iterates over two sets of elements in parallel.
+ *
+ *  The length of the first set determines the number of iteratsions.
+ */
+#define TEST_TEMPLATE_ELT2(arr_desc_elts_a,                     \
+                           arr_desc_elts_b,                     \
+                           elt_a_type, elt_b_type, output_type, \
+                           fut, fut_arg_interface,              \
+                           ref, ref_arg_interface,              \
+                           compare_interface)                   \
+        do                                                      \
+        {                                                       \
+            TEMPLATE_DO_ARR_DESC(                               \
+                elt_a_idx, elt_a_type, elt_a, arr_desc_elts_a   \
+                ,                                               \
+                elt_b_type * elt_b = ARR_DESC_ELT(              \
+                    elt_b_type,                                 \
+                    elt_a_idx,                                  \
+                    arr_desc_elts_b);                           \
+                                                                \
+                TEST_CALL_FUT_AND_REF(                          \
+                    fut, fut_arg_interface(                     \
+                        elt_a, elt_b),                          \
+                    ref, ref_arg_interface(                     \
+                        elt_a, elt_b));                         \
+                /* Comparison interfaces typically accept */    \
+                /* a block_size. Pass a dummy value 1.*/        \
+                compare_interface(1, output_type));             \
+            return JTEST_TEST_PASSED;                           \
+        } while (0)
+
+/**
+ *  Test template that uses an element and a block size.
+ */
+#define TEST_TEMPLATE_ELT1_BLK(arr_desc_elts,                       \
+                               arr_desc_block_sizes,                \
+                               elt_type, output_type,               \
+                               fut, fut_arg_interface,              \
+                               ref, ref_arg_interface,              \
+                               compare_interface)                   \
+        do                                                          \
+        {                                                           \
+            TEMPLATE_DO_ARR_DESC(                                   \
+                block_size_idx, uint32_t, block_size,               \
+                arr_desc_block_sizes                                \
+                ,                                                   \
+                TEMPLATE_DO_ARR_DESC(                               \
+                    elt_idx, elt_type, elt, arr_desc_elts           \
+                    ,                                               \
+                    JTEST_DUMP_STRF("Block Size: %d\n",             \
+                         (int)block_size);                          \
+                    TEST_CALL_FUT_AND_REF(                          \
+                        fut, fut_arg_interface(                     \
+                            elt, block_size),                       \
+                        ref, ref_arg_interface(                     \
+                            elt, block_size));                      \
+                    compare_interface(block_size, output_type)));   \
+            return JTEST_TEST_PASSED;                               \
+        } while (0)
+
+#endif /* _TEST_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_templates.h

+#ifndef _TRANSFORM_TEMPLATES_H_
+#define _TRANSFORM_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h>             /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Comparison SNR thresholds for the data types used in transform_tests.
+ */
+#define TRANSFORM_SNR_THRESHOLD_float32_t 90
+#define TRANSFORM_SNR_THRESHOLD_q31_t     90
+#define TRANSFORM_SNR_THRESHOLD_q15_t     30
+
+#define DCT4_TRANSFORM_SNR_THRESHOLD_float32_t 80
+#define DCT4_TRANSFORM_SNR_THRESHOLD_q31_t     75
+#define DCT4_TRANSFORM_SNR_THRESHOLD_q15_t     11
+
+/**
+ *  Compare the outputs from the function under test and the reference
+ *  function using SNR.
+ */
+#define TRANSFORM_SNR_COMPARE_INTERFACE(block_size,     \
+                                        output_type)    \
+    do                                                  \
+    {                                                   \
+        TEST_CONVERT_AND_ASSERT_SNR(                    \
+            transform_fft_output_f32_ref,               \
+            (output_type *) transform_fft_output_ref,   \
+            transform_fft_output_f32_fut,               \
+            (output_type *) transform_fft_output_fut,   \
+            block_size,                                 \
+            output_type,                                \
+            TRANSFORM_SNR_THRESHOLD_##output_type       \
+            );                                          \
+    } while (0)
+    
+/**
+ *  Compare the outputs from the function under test and the reference
+ *  function using SNR.
+ */
+#define DCT_TRANSFORM_SNR_COMPARE_INTERFACE(block_size,  \
+                                            output_type) \
+    do                                                   \
+    {                                                    \
+        TEST_CONVERT_AND_ASSERT_SNR(                     \
+            transform_fft_output_f32_ref,                \
+            (output_type *) transform_fft_output_ref,    \
+            transform_fft_output_f32_fut,                \
+            (output_type *) transform_fft_output_fut,    \
+            block_size,                                  \
+            output_type,                                 \
+            DCT4_TRANSFORM_SNR_THRESHOLD_##output_type   \
+            );                                           \
+    } while (0)                                           \
+
+/**
+ *  Specialization on #TRANSFORM_SNR_COMPARE_INTERFACE() to fix the block_size
+ *  for complex datasets.
+ */
+#define TRANSFORM_SNR_COMPARE_CMPLX_INTERFACE(block_size, output_type)  \
+    /* Complex numbers have two components*/                            \
+    TRANSFORM_SNR_COMPARE_INTERFACE(block_size * 2, output_type )
+
+/**
+ * This macro copys data from the input_ptr into input arrays.
+ *
+ * Some functions modify their input data; in order to provide the same data to
+ * multiple tests, copies must be made so the changes from one function don't
+ * impact the others.
+ */
+#define TRANSFORM_COPY_INPUTS(input_ptr,        \
+                              bytes)            \
+    do                                          \
+    {                                           \
+        memcpy(                                 \
+            transform_fft_input_fut,            \
+            input_ptr,                          \
+            bytes);                             \
+        memcpy(                                 \
+            transform_fft_input_ref,            \
+            input_ptr,                          \
+            bytes);                             \
+    } while (0)
+
+/**
+ * This macro copys data from the input_ptr into input arrays. It also creates
+ * symmetric input data for rfft inverse.
+ *
+ * The 4.534234f just makes the middle entry of the array semi random.  It's
+ * actual value doesn't seem to matter much.
+ *
+ * Some functions modify their input data; in order to provide the same data to
+ * multiple tests, copies must be made so the changes from one function don't
+ * impact the others.
+ */
+#define TRANSFORM_PREPARE_INVERSE_INPUTS(input_ptr,                              \
+                              fftlen, input_type, bytes)                         \
+    do                                                                           \
+    {                                                                            \
+        uint32_t i;                                                              \
+                                                                                 \
+        memcpy(                                                                  \
+            transform_fft_input_fut,                                             \
+            input_ptr,                                                           \
+            bytes);                                                              \
+                                                                                 \
+        ((input_type*)transform_fft_input_fut)[1] = 0;                           \
+        ((input_type*)transform_fft_input_fut)[fftlen + 0] = 0;                  \
+        ((input_type*)transform_fft_input_fut)[fftlen + 1] = 0;                  \
+        for(i=1;i<fftlen/2;i++)                                                  \
+        {                                                                        \
+           *((input_type*)transform_fft_input_fut + fftlen + 2*i + 0) =          \
+               *((input_type*)transform_fft_input_fut + fftlen - 2*i + 0);       \
+           *((input_type*)transform_fft_input_fut + fftlen + 2*i + 1) =          \
+               -(*((input_type*)transform_fft_input_fut + fftlen - 2*i + 1));    \
+                                                                                 \
+        }                                                                        \
+                                                                                 \
+        memcpy(                                                                  \
+            transform_fft_input_ref,                                             \
+            transform_fft_input_fut,                                             \
+            bytes * 2);                                                          \
+    } while (0)
+
+/**
+ * This macro copys data from the input_ptr into the in-place input arrays.
+ *
+ * Some functions modify their input data; in order to provide the same data to
+ * multiple tests, copies must be made so the changes from one function don't
+ * impact the others.
+ */
+#define TRANSFORM_PREPARE_INPLACE_INPUTS_DOWNSHIFT(input_ptr,       \
+                                         bytes,                     \
+                                         type)                      \
+    do                                                              \
+    {                                                               \
+        uint32_t i;                                                 \
+        memcpy(                                                     \
+            transform_fft_inplace_input_fut,                        \
+            input_ptr,                                              \
+            bytes);                                                 \
+        memcpy(                                                     \
+            transform_fft_inplace_input_ref,                        \
+            input_ptr,                                              \
+            bytes);                                                 \
+        for(i=0;i<bytes/sizeof(type);i++) {                         \
+            *((type*)transform_fft_inplace_input_fut + i) >>= 1;    \
+            *((type*)transform_fft_inplace_input_ref + i) >>= 1;}   \
+    } while (0)
+
+/**
+ * This macro copys data from the input_ptr into the in-place input arrays.
+ *
+ * Some functions modify their input data; in order to provide the same data to
+ * multiple tests, copies must be made so the changes from one function don't
+ * impact the others.
+ */
+#define TRANSFORM_PREPARE_INPLACE_INPUTS(input_ptr, \
+                                         bytes)     \
+    do                                              \
+    {                                               \
+        memcpy(                                     \
+            transform_fft_inplace_input_fut,        \
+            input_ptr,                              \
+            bytes);                                 \
+        memcpy(                                     \
+            transform_fft_inplace_input_ref,        \
+            input_ptr,                              \
+            bytes);                                 \
+    } while (0)
+
+
+#endif /* _TRANSFORM_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_data.h

+#ifndef _TRANSFORM_TEST_DATA_H_
+#define _TRANSFORM_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define TRANSFORM_MAX_FFT_LEN 4096
+#define TRANFORM_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+/* Lengths are multiplied by 2 to accomodate complex numbers*/
+extern float32_t transform_fft_output_fut[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_output_ref[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_input_fut[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_input_ref[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_output_f32_fut[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t transform_fft_output_f32_ref[TRANSFORM_MAX_FFT_LEN * 2];
+extern float32_t * transform_fft_inplace_input_fut;
+extern float32_t * transform_fft_inplace_input_ref;
+extern float32_t transform_fft_f32_inputs[TRANSFORM_MAX_FFT_LEN * 2];
+extern q31_t transform_fft_q31_inputs[TRANSFORM_MAX_FFT_LEN * 2];
+extern q15_t * transform_fft_q15_inputs;
+extern q15_t dct4_transform_fft_q15_inputs[TRANSFORM_MAX_FFT_LEN * 2];
+
+/* FFT Lengths */
+ARR_DESC_DECLARE(transform_radix2_fftlens);
+ARR_DESC_DECLARE(transform_radix4_fftlens);
+ARR_DESC_DECLARE(transform_rfft_fftlens);
+ARR_DESC_DECLARE(transform_rfft_fast_fftlens);
+ARR_DESC_DECLARE(transform_dct_fftlens);
+
+/* CFFT Structs */
+ARR_DESC_DECLARE(transform_cfft_f32_structs);
+ARR_DESC_DECLARE(transform_cfft_q31_structs);
+ARR_DESC_DECLARE(transform_cfft_q15_structs);
+
+#endif /* _TRANSFORM_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_test_group.h

+#ifndef _TRANSFORM_TEST_GROUP_H_
+#define _TRANSFORM_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(transform_tests);
+
+#endif /* _TRANSFORM_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/transform_tests/transform_tests.h

+#ifndef _TRANSFORM_TESTS_H_
+#define _TRANSFORM_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(cfft_tests);
+JTEST_DECLARE_GROUP(cfft_family_tests);
+JTEST_DECLARE_GROUP(dct4_tests);
+JTEST_DECLARE_GROUP(rfft_tests);
+JTEST_DECLARE_GROUP(rfft_fast_tests);
+
+#endif /* _TRANSFORM_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/type_abbrev.h

+#ifndef _TYPE_ABBREV_H_
+#define _TYPE_ABBREV_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Expand the abbreviation for a type into the type itself.
+ */
+#define TYPE_FROM_ABBREV(abbrev)                \
+    TYPE_ABBREV_##abbrev                        \
+
+/**
+ *  Expand the type to an abbreviation for that type.
+ *
+ *  Inverse of #TYPE_FROM_ABBREV().
+ *
+ *  @note Should be able to get a type back by writing.
+ *  TYPE_FROM_ABBREV(ABBREV_FROM_TYPE(type))
+ */
+#define ABBREV_FROM_TYPE(type)                  \
+    TYPE_SUFFIX_##type
+
+#define TYPE_ABBREV_f64 float64_t
+#define TYPE_ABBREV_f32 float32_t
+#define TYPE_ABBREV_q31 q31_t
+#define TYPE_ABBREV_q15 q15_t
+#define TYPE_ABBREV_q7  q7_t
+
+#define TYPE_SUFFIX_float64_t f64
+#define TYPE_SUFFIX_float32_t f32
+#define TYPE_SUFFIX_q31_t q31
+#define TYPE_SUFFIX_q15_t q15
+#define TYPE_SUFFIX_q7_t q7
+
+#endif /* _TYPE_ABBREV_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c

+/*----------------------------------------------------------------------------
+ * Name:    Retarget.c
+ * Purpose: 'Retarget' layer for target-dependent low level functions
+ * Note(s):
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2011 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include <rt_misc.h>
+#include "Serial.h"
+
+#pragma import(__use_no_semihosting_swi)
+
+
+
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+
+
+int fputc(int c, FILE *f) {
+  return (SER_PutChar(c));
+}
+
+
+int fgetc(FILE *f) {
+  return (SER_GetChar());
+}
+
+
+int ferror(FILE *f) {
+  /* Your implementation of ferror */
+  return EOF;
+}
+
+
+void _ttywrch(int c) {
+  SER_PutChar(c);
+}
+
+
+void _sys_exit(int return_code) {
+label:  goto label;  /* endless loop */
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s

+;/* File: startup_armv6-m.s
+; * Purpose: startup file for armv7-m architecture devices.
+; *          Should be used with ARMCC
+; * Version: V2.00
+; * Date: 16 November 2015
+; *
+; */
+;/* Copyright (c) 2011 - 2014 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+;/*
+;  //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                BKPT #0
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                BKPT #0
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+
+;/*
+;  __user_setup_stackheap() returns the:
+;     - heap base in r0 (if the program uses the heap)
+;     - stack base in sp
+;     - heap limit in r2 (if the program uses the heap and uses two-region memory).
+; */
+                EXPORT  __user_setup_stackheap
+
+__user_setup_stackheap PROC
+                LDR     R0, = __initial_sp
+                MOV     SP, R0
+				IF Heap_Size > 0
+                LDR     R2, = __heap_limit
+                LDR     R0, = __heap_base
+				ELSE
+                MOV     R0, #0
+                MOV     R2, #0
+                ENDIF
+                BX      LR
+                ENDP
+
+
+;/*
+;__user_initial_stackheap() returns the:
+;   - heap base in r0
+;   - stack base in r1, that is, the highest address in the stack region
+;   - heap limit in r2
+;   - stack limit in r3, that is, the lowest address in the stack region.
+; */
+;
+;/* DEPRICATED
+;                EXPORT  __user_initial_stackheap
+;
+;__user_initial_stackheap PROC
+;                LDR     R0, =  Heap_Mem
+;                LDR     R1, =(Stack_Mem + Stack_Size)
+;                LDR     R2, = (Heap_Mem +  Heap_Size)
+;                LDR     R3, = Stack_Mem
+;                BX      LR
+;                ENDP
+; */
+
+                ALIGN
+
+                ENDIF
+
+
+                END

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s

+;/* File: startup_armv7-m.s
+; * Purpose: startup file for armv7-m architecture devices.
+; *          Should be used with ARMCC
+; * Version: V2.00
+; * Date: 16 November 2015
+; *
+; */
+;/* Copyright (c) 2011 - 2014 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+;/*
+;  //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                BKPT #0
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                BKPT #0
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                BKPT #0
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                BKPT #0
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                BKPT #0
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+
+;/*
+;  __user_setup_stackheap() returns the:
+;     - heap base in r0 (if the program uses the heap)
+;     - stack base in sp
+;     - heap limit in r2 (if the program uses the heap and uses two-region memory).
+; */
+                EXPORT  __user_setup_stackheap
+
+__user_setup_stackheap PROC
+                LDR     R0, = __initial_sp
+                MOV     SP, R0
+				IF Heap_Size > 0
+                LDR     R2, = __heap_limit
+                LDR     R0, = __heap_base
+				ELSE
+                MOV     R0, #0
+                MOV     R2, #0
+                ENDIF
+                BX      LR
+                ENDP
+
+
+;/*
+;__user_initial_stackheap() returns the:
+;   - heap base in r0
+;   - stack base in r1, that is, the highest address in the stack region
+;   - heap limit in r2
+;   - stack limit in r3, that is, the lowest address in the stack region.
+; */
+;
+;/* DEPRICATED
+;                EXPORT  __user_initial_stackheap
+;
+;__user_initial_stackheap PROC
+;                LDR     R0, =  Heap_Mem
+;                LDR     R1, =(Stack_Mem + Stack_Size)
+;                LDR     R2, = (Heap_Mem +  Heap_Size)
+;                LDR     R3, = Stack_Mem
+;                BX      LR
+;                ENDP
+; */
+
+                ALIGN
+
+                ENDIF
+
+
+                END

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S

+/* File: startup_armv6-m.S
+ * Purpose: startup file for armv6-m architecture devices.
+ *          Should be used with ARMCLANG
+ * Version: V2.00
+ * Date: 16 November 2015
+ *
+ */
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+/*
+  ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+    .syntax unified
+    .arch   armv6-m
+
+/* .eabi_attribute Tag_ABI_align8_preserved,1    www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
+.eabi_attribute 25, 1   /* Tag_ABI_align_preserved */
+
+
+/*
+  ;<h> Stack Configuration
+  ;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  ;</h>
+*/
+    .equ    Stack_Size, 0x00000400
+
+    .section STACK, "w"
+    .align  3
+    .globl  __StackTop
+    .globl  __StackLimit
+__StackLimit:
+    .space  Stack_Size
+__StackTop:   /* formerly known as __initial_sp */
+
+
+/*
+  ;<h> Heap Configuration
+  ;  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  ;</h>
+*/
+    .equ    Heap_Size, 0x00000C00
+
+    .section HEAP, "w"
+    .align  3
+    .globl  __HeapBase
+    .globl  __HeapLimit
+__HeapBase:
+    .if Heap_Size
+    .space  Heap_Size
+    .endif
+__HeapLimit:
+
+
+    .section RESET, "x"
+    .align  2
+    .globl  __Vectors
+    .globl  __Vectors_End
+    .globl  __Vectors_Size
+__Vectors:
+    .long   __StackTop            /* Top of Stack */
+    .long   Reset_Handler         /* Reset Handler */
+    .long   NMI_Handler           /* NMI Handler */
+    .long   HardFault_Handler     /* Hard Fault Handler */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   SVC_Handler           /* SVCall Handler */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   PendSV_Handler        /* PendSV Handler */
+    .long   SysTick_Handler       /* SysTick Handler */
+__Vectors_End:
+
+    .equ    __Vectors_Size, __Vectors_End - __Vectors
+
+
+    .text
+    .thumb
+    .align  2
+
+    .globl  Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+    .thumb_func
+Reset_Handler:
+    bl      SystemInit
+    bl      __main
+
+    .globl  NMI_Handler
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+    .thumb_func
+NMI_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  HardFault_Handler
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+    .thumb_func
+HardFault_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  SVC_Handler
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+    .thumb_func
+SVC_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  PendSV_Handler
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+    .thumb_func
+PendSV_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  SysTick_Handler
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+    .thumb_func
+SysTick_Handler:
+    bkpt    #0
+    b       .
+
+
+    .global __use_two_region_memory
+
+/*
+  __user_setup_stackheap() returns the:
+     - heap base in r0 (if the program uses the heap)
+     - stack base in sp
+     - heap limit in r2 (if the program uses the heap and uses two-region memory).
+ */
+    .globl  __user_setup_stackheap
+    .type   __user_setup_stackheap, %function
+    .thumb_func
+__user_setup_stackheap:
+    ldr     r0, =__StackTop
+    mov     sp, r0
+    .if Heap_Size
+    ldr     r0, =__HeapBase
+    ldr     r2, =__HeapLimit
+    .else
+    mov     r0, #0
+    mov     r2, #0
+    .endif
+    bx      lr
+
+
+/*
+__user_initial_stackheap() returns the:
+   - heap base in r0
+   - stack base in r1, that is, the highest address in the stack region
+   - heap limit in r2
+   - stack limit in r3, that is, the lowest address in the stack region.
+ */
+/* DEPRICATED
+    .globl  __user_initial_stackheap
+    .type   __user_initial_stackheap, %function
+    .thumb_func
+__user_initial_stackheap:
+    ldr     r0, = __HeapBase
+    ldr     r1, = __StackTop
+    ldr     r2, = __HeapLimit
+    ldr     r3, = __StackLimit
+    bx      lr
+*/
+
+    .end

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S

+/* File: startup_armv7-m.S
+ * Purpose: startup file for armv7-m architecture devices.
+ *          Should be used with ARMCLANG
+ * Version: V2.00
+ * Date: 16 November 2015
+ *
+ */
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+/*
+  ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+    .syntax unified
+    .arch   armv6-m
+
+/* .eabi_attribute Tag_ABI_align8_preserved,1    www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
+.eabi_attribute 25, 1   /* Tag_ABI_align_preserved */
+
+
+/*
+  ;<h> Stack Configuration
+  ;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  ;</h>
+*/
+    .equ    Stack_Size, 0x00000400
+
+    .section STACK, "w"
+    .align  3
+    .globl  __StackTop
+    .globl  __StackLimit
+__StackLimit:
+    .space  Stack_Size
+__StackTop:   /* formerly known as __initial_sp */
+
+
+/*
+  ;<h> Heap Configuration
+  ;  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+  ;</h>
+*/
+    .equ    Heap_Size, 0x00000C00
+
+    .section HEAP, "w"
+    .align  3
+    .globl  __HeapBase
+    .globl  __HeapLimit
+__HeapBase:
+    .if Heap_Size
+    .space  Heap_Size
+    .endif
+__HeapLimit:
+
+
+    .section RESET, "x"
+    .align  2
+    .globl  __Vectors
+    .globl  __Vectors_End
+    .globl  __Vectors_Size
+__Vectors:
+    .long   __StackTop            /* Top of Stack */
+    .long   Reset_Handler         /* Reset Handler */
+    .long   NMI_Handler           /* NMI Handler */
+    .long   HardFault_Handler     /* Hard Fault Handler */
+    .long   MemManage_Handler     /* MPU Fault Handler */
+    .long   BusFault_Handler      /* Bus Fault Handler */
+    .long   UsageFault_Handler    /* Usage Fault Handler */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   SVC_Handler           /* SVCall Handler */
+    .long   DebugMon_Handler      /* Debug Monitor Handler */
+    .long   0                     /* Reserved */
+    .long   PendSV_Handler        /* PendSV Handler */
+    .long   SysTick_Handler       /* SysTick Handler */
+__Vectors_End:
+
+    .equ    __Vectors_Size, __Vectors_End - __Vectors
+
+
+    .text
+    .thumb
+    .align  2
+
+    .globl  Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+    .thumb_func
+Reset_Handler:
+    bl      SystemInit
+    bl      __main
+
+    .globl  NMI_Handler
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+    .thumb_func
+NMI_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  HardFault_Handler
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+    .thumb_func
+HardFault_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  MemManage_Handler
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+    .thumb_func
+MemManage_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  BusFault_Handler
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+    .thumb_func
+BusFault_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  UsageFault_Handler
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+    .thumb_func
+UsageFault_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  SVC_Handler
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+    .thumb_func
+SVC_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  DebugMon_Handler
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+    .thumb_func
+DebugMon_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  PendSV_Handler
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+    .thumb_func
+PendSV_Handler:
+    bkpt    #0
+    b       .
+
+    .globl  SysTick_Handler
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+    .thumb_func
+SysTick_Handler:
+    bkpt    #0
+    b       .
+
+
+    .global __use_two_region_memory
+
+/*
+  __user_setup_stackheap() returns the:
+     - heap base in r0 (if the program uses the heap)
+     - stack base in sp
+     - heap limit in r2 (if the program uses the heap and uses two-region memory).
+ */
+    .globl  __user_setup_stackheap
+    .type   __user_setup_stackheap, %function
+    .thumb_func
+__user_setup_stackheap:
+    ldr     r0, =__StackTop
+    mov     sp, r0
+    .if Heap_Size
+    ldr     r0, =__HeapBase
+    ldr     r2, =__HeapLimit
+    .else
+    mov     r0, #0
+    mov     r2, #0
+    .endif
+    bx      lr
+
+
+/*
+__user_initial_stackheap() returns the:
+   - heap base in r0
+   - stack base in r1, that is, the highest address in the stack region
+   - heap limit in r2
+   - stack limit in r3, that is, the lowest address in the stack region.
+ */
+/* DEPRICATED
+    .globl  __user_initial_stackheap
+    .type   __user_initial_stackheap, %function
+    .thumb_func
+__user_initial_stackheap:
+    ldr     r0, = __HeapBase
+    ldr     r1, = __StackTop
+    ldr     r2, = __HeapLimit
+    ldr     r3, = __StackLimit
+    bx      lr
+*/
+
+    .end

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c

+/*----------------------------------------------------------------------------
+ * Name:    Retarget.c
+ * Purpose: 'Retarget' layer for target-dependent low level functions
+ * Note(s):
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2012 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include <sys/stat.h>
+#include <string.h>
+#include <errno.h>
+
+int SER_PutChar (int c) {
+
+  return (c);
+}
+
+int SER_GetChar (void) {
+
+  return (-1);
+}
+
+/*-- GCC - Newlib runtime support --------------------------------------------*/
+
+extern int  __HeapBase;
+extern int  __HeapLimit;
+
+int _open (const char * path, int flags, ...) 
+{
+  return (-1);
+}
+
+int _close (int fd) 
+{
+  return (-1);
+}
+
+int _lseek (int fd, int ptr, int dir) 
+{
+  return (0);
+}
+
+int __attribute__((weak)) _fstat (int fd, struct stat * st) 
+{
+  memset (st, 0, sizeof (* st));
+  st->st_mode = S_IFCHR;
+  return (0);
+}
+
+int _isatty (int fd) 
+{
+  return (1);
+}
+
+int _read (int fd, char * ptr, int len) 
+{
+  char c;
+  int  i;
+
+  for (i = 0; i < len; i++) 
+  {
+    c = SER_GetChar();
+    if (c == 0x0D) break;
+    *ptr++ = c;
+    SER_PutChar(c);
+  }
+  return (len - i);
+}
+
+int _write (int fd, char * ptr, int len) 
+{
+  int i;
+
+  for (i = 0; i < len; i++) SER_PutChar (*ptr++);
+  return (i);
+}
+
+caddr_t _sbrk (int incr) 
+{
+  static char * heap;
+         char * prev_heap;
+
+  if (heap == NULL) 
+  {
+    heap = (char *)&__HeapBase;
+  }
+  
+  prev_heap = heap;
+
+  if ((heap + incr) > (char *)&__HeapLimit) 
+  {
+    errno = ENOMEM;
+    return (caddr_t) -1;
+  }
+  
+  heap += incr;
+
+  return (caddr_t) prev_heap;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S

+/* File: startup_armv6-m.S
+ * Purpose: startup file for armv6-m architecture devices.
+ *          Should be used with GCC for ARM Embedded Processors
+ * Version: V2.00
+ * Date: 16 November 2015
+ *
+ */
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+	.syntax	unified
+	.arch	armv6-m
+
+	.section .stack
+	.align	3
+#ifdef __STACK_SIZE
+	.equ	Stack_Size, __STACK_SIZE
+#else
+	.equ	Stack_Size, 0x00000400
+#endif
+	.globl	__StackTop
+	.globl	__StackLimit
+__StackLimit:
+	.space	Stack_Size
+	.size	__StackLimit, . - __StackLimit
+__StackTop:
+	.size	__StackTop, . - __StackTop
+
+	.section .heap
+	.align	3
+#ifdef __HEAP_SIZE
+	.equ	Heap_Size, __HEAP_SIZE
+#else
+	.equ	Heap_Size, 0x00000C00
+#endif
+	.globl	__HeapBase
+	.globl	__HeapLimit
+__HeapBase:
+	.if	Heap_Size
+	.space	Heap_Size
+	.endif
+	.size	__HeapBase, . - __HeapBase
+__HeapLimit:
+	.size	__HeapLimit, . - __HeapLimit
+
+	.section .vectors
+	.align 2
+	.globl	__Vectors
+__Vectors:
+	.long	__StackTop            /* Top of Stack */
+	.long	Reset_Handler         /* Reset Handler */
+	.long	NMI_Handler           /* NMI Handler */
+	.long	HardFault_Handler     /* Hard Fault Handler */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	SVC_Handler           /* SVCall Handler */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	PendSV_Handler        /* PendSV Handler */
+	.long	SysTick_Handler       /* SysTick Handler */
+
+	.size	__Vectors, . - __Vectors
+
+	.text
+	.thumb
+	.thumb_func
+	.align	1
+	.globl	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+	ldr	r4, =__copy_table_start__
+	ldr	r5, =__copy_table_end__
+
+.L_loop0:
+	cmp	r4, r5
+	bge	.L_loop0_done
+	ldr	r1, [r4]
+	ldr	r2, [r4, #4]
+	ldr	r3, [r4, #8]
+
+.L_loop0_0:
+	subs	r3, #4
+	blt	.L_loop0_0_done
+	ldr	r0, [r1, r3]
+	str	r0, [r2, r3]
+	b	.L_loop0_0
+
+.L_loop0_0_done:
+	adds	r4, #12
+	b	.L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+	ldr	r1, =__etext
+	ldr	r2, =__data_start__
+	ldr	r3, =__data_end__
+
+	subs	r3, r2
+	ble	.L_loop1_done
+
+.L_loop1:
+	subs	r3, #4
+	ldr	r0, [r1,r3]
+	str	r0, [r2,r3]
+	bgt	.L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+	ldr	r3, =__zero_table_start__
+	ldr	r4, =__zero_table_end__
+
+.L_loop2:
+	cmp	r3, r4
+	bge	.L_loop2_done
+	ldr	r1, [r3]
+	ldr	r2, [r3, #4]
+	movs	r0, 0
+
+.L_loop2_0:
+	subs	r2, #4
+	blt	.L_loop2_0_done
+	str	r0, [r1, r2]
+	b	.L_loop2_0
+.L_loop2_0_done:
+
+	adds	r3, #8
+	b	.L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+	ldr	r1, =__bss_start__
+	ldr	r2, =__bss_end__
+
+	movs	r0, 0
+
+	subs	r2, r1
+	ble	.L_loop3_done
+
+.L_loop3:
+	subs	r2, #4
+	str	r0, [r1, r2]
+	bgt	.L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+	bl	SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+	bl	__START
+
+	.pool
+	.size	Reset_Handler, . - Reset_Handler
+
+	.align	1
+	.thumb_func
+	.weak	Default_Handler
+	.type	Default_Handler, %function
+Default_Handler:
+    bkpt #0
+	b	.
+	.size	Default_Handler, . - Default_Handler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+	.macro	def_irq_handler	handler_name
+	.weak	\handler_name
+	.set	\handler_name, Default_Handler
+	.endm
+
+	def_irq_handler	NMI_Handler
+	def_irq_handler	HardFault_Handler
+	def_irq_handler	SVC_Handler
+	def_irq_handler	PendSV_Handler
+	def_irq_handler	SysTick_Handler
+
+	.end

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S

+/* File: startup_armv7-m.S
+ * Purpose: startup file for armv7-m architecture devices.
+ *          Should be used with GCC for ARM Embedded Processors
+ * Version: V2.00
+ * Date: 16 November 2015
+ *
+ */
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+	.syntax	unified
+	.arch	armv7-m
+
+	.section .stack
+	.align	3
+#ifdef __STACK_SIZE
+	.equ	Stack_Size, __STACK_SIZE
+#else
+	.equ	Stack_Size, 0x00000400
+#endif
+	.globl	__StackTop
+	.globl	__StackLimit
+__StackLimit:
+	.space	Stack_Size
+	.size	__StackLimit, . - __StackLimit
+__StackTop:
+	.size	__StackTop, . - __StackTop
+
+	.section .heap
+	.align	3
+#ifdef __HEAP_SIZE
+	.equ	Heap_Size, __HEAP_SIZE
+#else
+	.equ	Heap_Size, 0x00000C00
+#endif
+	.globl	__HeapBase
+	.globl	__HeapLimit
+__HeapBase:
+	.if	Heap_Size
+	.space	Heap_Size
+	.endif
+	.size	__HeapBase, . - __HeapBase
+__HeapLimit:
+	.size	__HeapLimit, . - __HeapLimit
+
+	.section .vectors
+	.align	2
+	.globl	__Vectors
+__Vectors:
+	.long	__StackTop            /* Top of Stack */
+	.long	Reset_Handler         /* Reset Handler */
+	.long	NMI_Handler           /* NMI Handler */
+	.long	HardFault_Handler     /* Hard Fault Handler */
+	.long	MemManage_Handler     /* MPU Fault Handler */
+	.long	BusFault_Handler      /* Bus Fault Handler */
+	.long	UsageFault_Handler    /* Usage Fault Handler */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	0                     /* Reserved */
+	.long	SVC_Handler           /* SVCall Handler */
+	.long	DebugMon_Handler      /* Debug Monitor Handler */
+	.long	0                     /* Reserved */
+	.long	PendSV_Handler        /* PendSV Handler */
+	.long	SysTick_Handler       /* SysTick Handler */
+
+	.size	__Vectors, . - __Vectors
+
+	.text
+	.thumb
+	.thumb_func
+	.align	2
+	.globl	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+	ldr	r4, =__copy_table_start__
+	ldr	r5, =__copy_table_end__
+
+.L_loop0:
+	cmp	r4, r5
+	bge	.L_loop0_done
+	ldr	r1, [r4]
+	ldr	r2, [r4, #4]
+	ldr	r3, [r4, #8]
+
+.L_loop0_0:
+	subs	r3, #4
+	ittt	ge
+	ldrge	r0, [r1, r3]
+	strge	r0, [r2, r3]
+	bge	.L_loop0_0
+
+	adds	r4, #12
+	b	.L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+	ldr	r1, =__etext
+	ldr	r2, =__data_start__
+	ldr	r3, =__data_end__
+
+.L_loop1:
+	cmp	r2, r3
+	ittt	lt
+	ldrlt	r0, [r1], #4
+	strlt	r0, [r2], #4
+	blt	.L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+	ldr	r3, =__zero_table_start__
+	ldr	r4, =__zero_table_end__
+
+.L_loop2:
+	cmp	r3, r4
+	bge	.L_loop2_done
+	ldr	r1, [r3]
+	ldr	r2, [r3, #4]
+	movs	r0, 0
+
+.L_loop2_0:
+	subs	r2, #4
+	itt	ge
+	strge	r0, [r1, r2]
+	bge	.L_loop2_0
+
+	adds	r3, #8
+	b	.L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+	ldr	r1, =__bss_start__
+	ldr	r2, =__bss_end__
+
+	movs	r0, 0
+.L_loop3:
+	cmp	r1, r2
+	itt	lt
+	strlt	r0, [r1], #4
+	blt	.L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+	bl	SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+	bl	__START
+
+	.pool
+	.size	Reset_Handler, . - Reset_Handler
+
+	.align	1
+	.thumb_func
+	.weak	Default_Handler
+	.type	Default_Handler, %function
+Default_Handler:
+    bkpt #0
+	b	.
+	.size	Default_Handler, . - Default_Handler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+	.macro	def_irq_handler	handler_name
+	.weak	\handler_name
+	.set	\handler_name, Default_Handler
+	.endm
+
+	def_irq_handler	NMI_Handler
+	def_irq_handler	HardFault_Handler
+	def_irq_handler	MemManage_Handler
+	def_irq_handler	BusFault_Handler
+	def_irq_handler	UsageFault_Handler
+	def_irq_handler	SVC_Handler
+	def_irq_handler	DebugMon_Handler
+	def_irq_handler	PendSV_Handler
+	def_irq_handler	SysTick_Handler
+
+	.end

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S

+
+#if defined (__CC_ARM)
+  #if   (defined (ARM_MATH_CM0))
+    #include "ARMCC\startup_armv6-m.s"
+  #elif (defined (ARM_MATH_CM0P))
+    #include "ARMCC\startup_armv6-m.s"
+  #elif (defined (ARM_MATH_CM3))
+    #include "ARMCC\startup_armv7-m.s"
+  #elif (defined (ARM_MATH_CM4))
+    #include "ARMCC\startup_armv7-m.s"
+  #elif (defined (ARM_MATH_CM7))
+    #include "ARMCC\startup_armv7-m.s"
+  #elif (defined (ARM_MATH_ARMV8MBL))
+    #include "ARMCC\startup_armv6-m.s"
+  #elif (defined (ARM_MATH_ARMV8MML))
+    #include "ARMCC\startup_armv7-m.s"
+  #else
+    #error "No appropriate startup file found!"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if   (defined (ARM_MATH_CM0))
+    #include "ARMCLANG\startup_armv6-m.S"
+  #elif (defined (ARM_MATH_CM0P))
+    #include "ARMCLANG\startup_armv6-m.S"
+  #elif (defined (ARM_MATH_CM3))
+    #include "ARMCLANG\startup_armv7-m.S"
+  #elif (defined (ARM_MATH_CM4))
+    #include "ARMCLANG\startup_armv7-m.S"
+  #elif (defined (ARM_MATH_CM7))
+    #include "ARMCLANG\startup_armv7-m.S"
+  #elif (defined (ARM_MATH_ARMV8MBL))
+    #include "ARMCLANG\startup_armv6-m.S"
+  #elif (defined (ARM_MATH_ARMV8MML))
+    #include "ARMCLANG\startup_armv7-m.S"
+  #else
+    #error "No appropriate startup file found!"
+  #endif
+
+#elif defined (__GNUC__)
+  #if   (defined (ARM_MATH_CM0))
+    #include "GCC\startup_armv6-m.S"
+  #elif (defined (ARM_MATH_CM0P))
+    #include "GCC\startup_armv6-m.S"
+  #elif (defined (ARM_MATH_CM3))
+    #include "GCC\startup_armv7-m.S"
+  #elif (defined (ARM_MATH_CM4))
+    #include "GCC\startup_armv7-m.S"
+  #elif (defined (ARM_MATH_CM7))
+    #include "GCC\startup_armv7-m.S"
+  #elif (defined (ARM_MATH_ARMV8MBL))
+    #include "GCC\startup_armv6-m.S"
+  #elif (defined (ARM_MATH_ARMV8MML))
+    #include "GCC\startup_armv7-m.S"
+  #else
+    #error "No appropriate startup file found!"
+  #endif
+
+#else
+  #error "Compiler not supported!"
+#endif
+

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c

+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM0 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c

+/**************************************************************************//**
+ * @file     system_ARMCM23.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM23 Device Series
+ * @version  V5.00
+ * @date     21. October 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM23)
+  #include "ARMCM23.h"
+#elif defined (ARMCM23_TZ)
+  #include "ARMCM23_TZ.h"
+
+  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+    #include "partition_ARMCM23.h"
+  #endif
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  TZ_SAU_Setup();
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c

+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM3 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c

+/**************************************************************************//**
+ * @file     system_ARMCM33.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM33 Device Series
+ * @version  V5.00
+ * @date     02. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+  #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+  #include "ARMCM33_TZ.h"
+
+  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+    #include "partition_ARMCM33.h"
+  #endif
+#elif defined (ARMCM33_DSP_FP)
+  #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+  #include "ARMCM33_DSP_FP_TZ.h"
+
+  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+    #include "partition_ARMCM33.h"
+  #endif
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  TZ_SAU_Setup();
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c

+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM4 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+  #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+  #include "ARMCM4_FP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c

+/**************************************************************************//**
+ * @file     system_ARMCM7.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+  #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+  #include "ARMCM7_DP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c

+/**************************************************************************//**
+ * @file     system_ARMSC000.c
+ * @brief    CMSIS Device System Source File for
+ *           for ARMSC000 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMSC000.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c

+/**************************************************************************//**
+ * @file     system_ARMSC300.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMSC300 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMSC300.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c

+/**************************************************************************//**
+ * @file     system_ARMv8MBL.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMv8MBL Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMv8MBL.h"
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+  #include "partition_ARMv8MBL.h"
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  TZ_SAU_Setup();
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c

+/**************************************************************************//**
+ * @file     system_ARMv8MML.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMv8MML Device Series
+ * @version  V5.00
+ * @date     02. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMv8MML)
+  #include "ARMv8MML.h"
+#elif defined (ARMv8MML_DSP)
+  #include "ARMv8MML_DSP.h"
+#elif defined (ARMv8MML_SP)
+  #include "ARMv8MML_SP.h"
+#elif defined (ARMv8MML_DSP_SP)
+  #include "ARMv8MML_DSP_SP.h"
+#elif defined (ARMv8MML_DP)
+  #include "ARMv8MML_DP.h"
+#elif defined (ARMv8MML_DSP_DP)
+  #include "ARMv8MML_DSP_DP.h"
+#else
+  #error device not specified!
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+  #include "partition_ARMv8MML.h"
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  TZ_SAU_Setup();
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c

+
+#if   (defined (ARMCM0))
+  #include "system_ARMCM0.c"
+
+#elif (defined (ARMCM0P))
+  #include "system_ARMCM0plus.c"
+
+#elif (defined (ARMCM3))
+  #include "system_ARMCM3.c"
+
+#elif (defined (ARMCM4) || defined (ARMCM4_FP))
+  #include "system_ARMCM4.c"
+
+#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP))
+  #include "system_ARMCM7.c"
+
+#elif defined (ARMv8MBL)
+  #include "system_ARMv8MBL.c"
+
+#elif (defined (ARMv8MML)    || defined (ARMv8MML_DSP)    || \
+       defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \
+       defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP)   )
+  #include "system_ARMv8MML.c"
+
+#else
+  #error "No appropriate system file found!"
+#endif

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c

+#include "jtest.h"
+#include "basic_math_test_group.h"
+#include "complex_math_test_group.h"
+#include "controller_test_group.h"
+#include "fast_math_test_group.h"
+#include "filtering_test_group.h"
+#include "matrix_test_group.h"
+#include "statistics_test_group.h"
+#include "support_test_group.h"
+#include "transform_test_group.h"
+#include "intrinsics_test_group.h"
+
+JTEST_DEFINE_GROUP(all_tests)
+{
+    /*
+      To skip a test, comment it out
+    */
+    JTEST_GROUP_CALL(basic_math_tests);
+    JTEST_GROUP_CALL(complex_math_tests);
+    JTEST_GROUP_CALL(controller_tests);
+    JTEST_GROUP_CALL(fast_math_tests);
+    JTEST_GROUP_CALL(filtering_tests);
+    JTEST_GROUP_CALL(matrix_tests);
+    JTEST_GROUP_CALL(statistics_tests);
+    JTEST_GROUP_CALL(support_tests);
+    JTEST_GROUP_CALL(transform_tests);
+    JTEST_GROUP_CALL(intrinsics_tests);
+
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_ABS_TEST(suffix)              \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(   \
+        abs,                                    \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix))
+    
+JTEST_ARM_ABS_TEST(f32);
+JTEST_ARM_ABS_TEST(q31);
+JTEST_ARM_ABS_TEST(q15);
+JTEST_ARM_ABS_TEST(q7 );
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(abs_tests)
+{
+    JTEST_TEST_CALL(arm_abs_f32_test);
+    JTEST_TEST_CALL(arm_abs_q31_test);
+    JTEST_TEST_CALL(arm_abs_q15_test);
+    JTEST_TEST_CALL(arm_abs_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_ADD_TEST(suffix)              \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(   \
+        add,                                    \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        BASIC_MATH_COMPARE_INTERFACE)
+
+JTEST_ARM_ADD_TEST(f32);
+JTEST_ARM_ADD_TEST(q31);
+JTEST_ARM_ADD_TEST(q15);
+JTEST_ARM_ADD_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(add_tests)
+{
+    JTEST_TEST_CALL(arm_add_f32_test);
+    JTEST_TEST_CALL(arm_add_q31_test);
+    JTEST_TEST_CALL(arm_add_q15_test);
+    JTEST_TEST_CALL(arm_add_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c

+#include "basic_math_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(BASIC_MATH_BIGGEST_INPUT_TYPE,
+                basic_math_output_fut,
+                BASIC_MATH_MAX_INPUT_ELEMENTS,
+                CURLY(0));
+
+ARR_DESC_DEFINE(BASIC_MATH_BIGGEST_INPUT_TYPE,
+                basic_math_output_ref,
+                BASIC_MATH_MAX_INPUT_ELEMENTS,
+                CURLY(0));
+
+BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+/*--------------------------------------------------------------------------------*/
+/* Block Sizes */
+/*--------------------------------------------------------------------------------*/
+
+/* 
+  To change test parameter values add/remove values inside CURLY and update 
+  the preceeding parameter to reflect the number of values inside CURLY. 
+*/
+
+ARR_DESC_DEFINE(uint32_t,
+                basic_math_block_sizes,
+                4,
+                CURLY( 2, 7, 15, 32));
+
+/*--------------------------------------------------------------------------------*/
+/* Numbers */
+/*--------------------------------------------------------------------------------*/
+
+/* 
+  To change test parameter values add/remove values inside CURLY and update 
+  the preceeding parameter to reflect the number of values inside CURLY. 
+*/
+
+ARR_DESC_DEFINE(uint32_t,
+                basic_math_elts,
+                4,
+                CURLY( 0, 1, 0x80000000, 0x7fffffff));
+
+ARR_DESC_DEFINE(int8_t,
+                basic_math_elts2,
+                5,
+                CURLY( 0, 3, -3, -7, 7));
+
+ARR_DESC_DEFINE(float32_t,
+                basic_math_eltsf,
+                6,
+                CURLY( 0.0f, 1.0f, 1.254001, -1.665584, -127.435646, 245.34634267));
+
+/*--------------------------------------------------------------------------------*/
+/* Test Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+                basic_math_f_32,
+                32,
+                CURLY(
+                      -0.432565, -1.665584,  0.125332,  0.287676, -1.146471,
+                       1.190915,  1.189164, -0.037633,  0.327292,  0.174639,
+                      -0.186709,  0.725791, -0.588317,  2.183186, -0.136396,
+                       0.113931,  1.066768,  0.059281, -0.095648, -0.832349,
+                       0.294411, -1.336182,  0.714325,  1.623562, -0.691776,
+                       0.857997,  1.254001, -1.593730, -1.440964,  0.571148,
+                      -0.399886,  0.689997
+                      ));
+
+/* Alias the 32 element array with wrappers that end sooner. */
+ARR_DESC_DEFINE_SUBSET(basic_math_f_15,
+                       basic_math_f_32,
+                       15);
+
+ARR_DESC_DEFINE_SUBSET(basic_math_f_2,
+                       basic_math_f_32,
+                       2);
+
+ARR_DESC_DEFINE(float32_t,
+                basic_math_zeros,
+                32,
+                CURLY(0));
+
+/* Aggregate all float datasets. */
+ARR_DESC_DEFINE(ARR_DESC_t *,
+                basic_math_f_all,
+                4,
+                CURLY(
+                      &basic_math_zeros,
+                      &basic_math_f_2,
+                      &basic_math_f_15,
+                      &basic_math_f_32
+                      ));

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c

+#include "jtest.h"
+#include "basic_math_tests.h"
+
+JTEST_DEFINE_GROUP(basic_math_tests)
+{
+    JTEST_GROUP_CALL(abs_tests);
+    JTEST_GROUP_CALL(add_tests);
+    JTEST_GROUP_CALL(dot_prod_tests);
+    JTEST_GROUP_CALL(mult_tests);
+    JTEST_GROUP_CALL(negate_tests);
+    JTEST_GROUP_CALL(offset_tests);
+    JTEST_GROUP_CALL(scale_tests); 
+    JTEST_GROUP_CALL(shift_tests);
+    JTEST_GROUP_CALL(sub_tests);
+
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_DOT_PROD_TEST(suffix)         \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(   \
+        dot_prod,                               \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE)
+
+JTEST_ARM_DOT_PROD_TEST(f32);
+JTEST_ARM_DOT_PROD_TEST(q31);
+JTEST_ARM_DOT_PROD_TEST(q15);
+JTEST_ARM_DOT_PROD_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(dot_prod_tests)
+{
+    JTEST_TEST_CALL(arm_dot_prod_f32_test);
+    JTEST_TEST_CALL(arm_dot_prod_q31_test);
+    JTEST_TEST_CALL(arm_dot_prod_q15_test);
+    JTEST_TEST_CALL(arm_dot_prod_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MULT_TEST(suffix, compare_interface)  \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(   \
+        mult,                                   \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        compare_interface)
+
+JTEST_ARM_MULT_TEST(f32, BASIC_MATH_COMPARE_INTERFACE);
+JTEST_ARM_MULT_TEST(q31, BASIC_MATH_SNR_COMPARE_INTERFACE);
+JTEST_ARM_MULT_TEST(q15, BASIC_MATH_COMPARE_INTERFACE);
+JTEST_ARM_MULT_TEST(q7 , BASIC_MATH_COMPARE_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mult_tests)
+{
+    JTEST_TEST_CALL(arm_mult_f32_test);
+    JTEST_TEST_CALL(arm_mult_q31_test);
+    JTEST_TEST_CALL(arm_mult_q15_test);
+    JTEST_TEST_CALL(arm_mult_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_NEGATE_TEST(suffix)           \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(   \
+        negate,                                 \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix))
+    
+JTEST_ARM_NEGATE_TEST(f32);
+JTEST_ARM_NEGATE_TEST(q31);
+JTEST_ARM_NEGATE_TEST(q15);
+JTEST_ARM_NEGATE_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(negate_tests)
+{
+    JTEST_TEST_CALL(arm_negate_f32_test);
+    JTEST_TEST_CALL(arm_negate_q31_test);
+    JTEST_TEST_CALL(arm_negate_q15_test);
+    JTEST_TEST_CALL(arm_negate_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_OFFSET_TEST(suffix)               \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK(  \
+        offset,                                     \
+        suffix,                                     \
+        TYPE_FROM_ABBREV(suffix),                   \
+        TYPE_FROM_ABBREV(suffix),                   \
+        TYPE_FROM_ABBREV(suffix))
+
+JTEST_ARM_OFFSET_TEST(f32);
+JTEST_ARM_OFFSET_TEST(q31);
+JTEST_ARM_OFFSET_TEST(q15);
+JTEST_ARM_OFFSET_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(offset_tests)
+{
+    JTEST_TEST_CALL(arm_offset_f32_test);
+    JTEST_TEST_CALL(arm_offset_q31_test);
+    JTEST_TEST_CALL(arm_offset_q15_test);
+    JTEST_TEST_CALL(arm_offset_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+
+#define JTEST_ARM_SCALE_TEST(suffix)                \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK(  \
+        scale,                                      \
+        suffix,                                     \
+        TYPE_FROM_ABBREV(suffix),                   \
+        TYPE_FROM_ABBREV(suffix), /*elt1_type*/     \
+        int8_t, /*elt2_type*/                       \
+        TYPE_FROM_ABBREV(suffix))
+
+/* float32_t defined separately because it has less arguments */
+JTEST_DEFINE_TEST(arm_scale_f32_test,
+                  arm_scale_f32)
+{
+    TEST_TEMPLATE_BUF1_ELT1_BLK(
+        basic_math_f_all,
+        basic_math_eltsf,
+        basic_math_block_sizes,
+        float32_t,
+        float32_t,
+        float32_t,
+        arm_scale_f32,
+        ARM_scale_float_INPUT_INTERFACE,
+        ref_scale_f32,
+        REF_scale_float_INPUT_INTERFACE,
+        BASIC_MATH_COMPARE_INTERFACE);
+}
+
+JTEST_ARM_SCALE_TEST(q31);
+JTEST_ARM_SCALE_TEST(q15);
+JTEST_ARM_SCALE_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(scale_tests)
+{
+    JTEST_TEST_CALL(arm_scale_f32_test);
+    JTEST_TEST_CALL(arm_scale_q31_test);
+    JTEST_TEST_CALL(arm_scale_q15_test);
+    JTEST_TEST_CALL(arm_scale_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_SHIFT_TEST(suffix)                \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK(  \
+        shift,                                      \
+        suffix,                                     \
+        TYPE_FROM_ABBREV(suffix),                   \
+        int8_t, /*elt_type*/                        \
+        TYPE_FROM_ABBREV(suffix))
+
+JTEST_ARM_SHIFT_TEST(q31);
+JTEST_ARM_SHIFT_TEST(q15);
+JTEST_ARM_SHIFT_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(shift_tests)
+{
+    JTEST_TEST_CALL(arm_shift_q31_test);
+    JTEST_TEST_CALL(arm_shift_q15_test);
+    JTEST_TEST_CALL(arm_shift_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c

+#include "jtest.h"
+#include "basic_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "basic_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_SUB_TEST(suffix)              \
+    BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(   \
+        sub,                                    \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        BASIC_MATH_COMPARE_INTERFACE)
+
+JTEST_ARM_SUB_TEST(f32);
+JTEST_ARM_SUB_TEST(q31);
+JTEST_ARM_SUB_TEST(q15);
+JTEST_ARM_SUB_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(sub_tests)
+{
+    JTEST_TEST_CALL(arm_sub_f32_test);
+    JTEST_TEST_CALL(arm_sub_q31_test);
+    JTEST_TEST_CALL(arm_sub_q15_test);
+    JTEST_TEST_CALL(arm_sub_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c

+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_CONJ_TEST(suffix)           \
+    COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(     \
+        cmplx_conj,                                 \
+        suffix,                                     \
+        TYPE_FROM_ABBREV(suffix),                   \
+        TYPE_FROM_ABBREV(suffix),                   \
+        COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE)
+
+JTEST_ARM_CMPLX_CONJ_TEST(f32);
+JTEST_ARM_CMPLX_CONJ_TEST(q31);
+JTEST_ARM_CMPLX_CONJ_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_conj_tests)
+{
+    JTEST_TEST_CALL(arm_cmplx_conj_f32_test);
+    JTEST_TEST_CALL(arm_cmplx_conj_q31_test);
+    JTEST_TEST_CALL(arm_cmplx_conj_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c

+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_DOT_PROD_TEST(suffix, comparison_interface) \
+    COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(                     \
+        cmplx_dot_prod,                                             \
+        suffix,                                                     \
+        TYPE_FROM_ABBREV(suffix),                                   \
+        TYPE_FROM_ABBREV(suffix),                                   \
+        comparison_interface)
+
+JTEST_ARM_CMPLX_DOT_PROD_TEST(f32, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE);
+JTEST_ARM_CMPLX_DOT_PROD_TEST(q31, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE);
+JTEST_ARM_CMPLX_DOT_PROD_TEST(q15, COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_dot_prod_tests)
+{
+    JTEST_TEST_CALL(arm_cmplx_dot_prod_f32_test);
+    JTEST_TEST_CALL(arm_cmplx_dot_prod_q31_test);
+    JTEST_TEST_CALL(arm_cmplx_dot_prod_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c

+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_MAG_SQUARED_TEST(suffix)    \
+    COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(     \
+        cmplx_mag_squared,                          \
+        suffix,                                     \
+        TYPE_FROM_ABBREV(suffix),                   \
+        TYPE_FROM_ABBREV(suffix),                   \
+        COMPLEX_MATH_COMPARE_RE_INTERFACE)
+
+JTEST_ARM_CMPLX_MAG_SQUARED_TEST(f32);
+JTEST_ARM_CMPLX_MAG_SQUARED_TEST(q31);
+JTEST_ARM_CMPLX_MAG_SQUARED_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_mag_squared_tests)
+{
+    JTEST_TEST_CALL(arm_cmplx_mag_squared_f32_test);
+    JTEST_TEST_CALL(arm_cmplx_mag_squared_q31_test);
+    JTEST_TEST_CALL(arm_cmplx_mag_squared_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c

+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_MAG_TEST(suffix, comparison_interface)  \
+    COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(                 \
+        cmplx_mag,                                              \
+        suffix,                                                 \
+        TYPE_FROM_ABBREV(suffix),                               \
+        TYPE_FROM_ABBREV(suffix),                               \
+        comparison_interface)
+
+JTEST_ARM_CMPLX_MAG_TEST(f32, COMPLEX_MATH_COMPARE_RE_INTERFACE);
+JTEST_ARM_CMPLX_MAG_TEST(q31, COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE);
+JTEST_ARM_CMPLX_MAG_TEST(q15, COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_mag_tests)
+{
+    JTEST_TEST_CALL(arm_cmplx_mag_f32_test);
+    JTEST_TEST_CALL(arm_cmplx_mag_q31_test);
+    JTEST_TEST_CALL(arm_cmplx_mag_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c

+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_MULT_CMPLX_TEST(suffix) \
+    COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK( \
+        cmplx_mult_cmplx,                       \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        COMPLEX_MATH_COMPARE_CMPLX_INTERFACE)
+
+JTEST_ARM_CMPLX_MULT_CMPLX_TEST(f32);
+JTEST_ARM_CMPLX_MULT_CMPLX_TEST(q31);
+JTEST_ARM_CMPLX_MULT_CMPLX_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_mult_cmplx_tests)
+{
+    JTEST_TEST_CALL(arm_cmplx_mult_cmplx_f32_test);
+    JTEST_TEST_CALL(arm_cmplx_mult_cmplx_q31_test);
+    JTEST_TEST_CALL(arm_cmplx_mult_cmplx_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c

+#include "jtest.h"
+#include "complex_math_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "complex_math_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_CMPLX_MULT_REAL_TEST(suffix, comparison_interface)    \
+    COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(                         \
+        cmplx_mult_real,                                                \
+        suffix,                                                         \
+        TYPE_FROM_ABBREV(suffix),                                       \
+        TYPE_FROM_ABBREV(suffix),                                       \
+        comparison_interface)
+
+JTEST_ARM_CMPLX_MULT_REAL_TEST(f32, COMPLEX_MATH_COMPARE_CMPLX_INTERFACE);
+JTEST_ARM_CMPLX_MULT_REAL_TEST(q31, COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE);
+JTEST_ARM_CMPLX_MULT_REAL_TEST(q15, COMPLEX_MATH_COMPARE_CMPLX_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(cmplx_mult_real_tests)
+{
+    JTEST_TEST_CALL(arm_cmplx_mult_real_f32_test);
+    JTEST_TEST_CALL(arm_cmplx_mult_real_q31_test);
+    JTEST_TEST_CALL(arm_cmplx_mult_real_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c

+#include "complex_math_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE,
+                complex_math_output_fut_a,
+                COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/,
+                CURLY(0));
+
+ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE,
+                complex_math_output_fut_b,
+                COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/,
+                CURLY(0));
+
+ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE,
+                complex_math_output_ref_a,
+                COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/,
+                CURLY(0));
+
+
+ARR_DESC_DEFINE(COMPLEX_MATH_BIGGEST_INPUT_TYPE,
+                complex_math_output_ref_b,
+                COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2 /*Complex data has two parts*/,
+                CURLY(0));
+
+
+COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+/*--------------------------------------------------------------------------------*/
+/* Block Sizes */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(uint32_t,
+                complex_math_block_sizes,
+                4,
+                CURLY(1, 2, 15, 32));
+
+/*--------------------------------------------------------------------------------*/
+/* Test Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+                complex_math_f_32,
+                32 * 2 /*Complex data has two parts*/,
+                CURLY(
+                      -0.432564811528220680 ,	0.815622288876143300,	
+                      -1.665584378238097000 ,	0.711908323500893280,	
+                      0.125332306474830680  ,	1.290249754932477000,	
+                      0.287676420358548850  ,	0.668600505682040320,	
+                      -1.146471350681463700 ,	1.190838074243369100,	
+                      1.190915465642998800  ,	-1.202457114773944000,	
+                      1.189164201652103100  ,	-0.019789557768770449,	
+                      -0.037633276593317645 ,	-0.156717298831980680,	
+                      0.327292361408654140  ,	-1.604085562001158500,	
+                      0.174639142820924520  ,	0.257304234677489860,	
+                      -0.186708577681439360 ,	-1.056472928081482400,	
+                      0.725790548293302700  ,	1.415141485872338600,	
+                      -0.588316543014188680 ,	-0.805090404196879830,	
+                      2.183185818197101100  ,	0.528743010962224870,	
+                      -0.136395883086595700 ,	0.219320672667622370,	
+                      0.113931313520809620  ,	-0.921901624355539130,	
+                      1.066768211359188800  ,	-2.170674494305262500,	
+                      0.059281460523605348  ,	-0.059187824521191180,	
+                      -0.095648405483669041 ,	-1.010633706474247400,	
+                      -0.832349463650022490 ,	0.614463048895480980,	
+                      0.294410816392640380  ,	0.507740785341985520,	
+                      -1.336181857937804000 ,	1.692429870190521400,	
+                      0.714324551818952160  ,	0.591282586924175900,	
+                      1.623562064446270700  ,	-0.643595202682526120,	
+                      -0.691775701702286750 ,	0.380337251713910140,	
+                      0.857996672828262640  ,	-1.009115524340785000,	
+                      1.254001421602532400  ,	-0.019510669530289293,	
+                      -1.593729576447476800 ,	-0.048220789145312269,	
+                      -1.440964431901020000 ,	0.000043191841625545,	
+                      0.571147623658177950  ,	-0.317859451247687890,	
+                      -0.399885577715363150 ,	1.095003738787492500,	
+                      0.689997375464345140  ,	-1.873990257640960800
+                      ));
+
+ARR_DESC_DEFINE_SUBSET(complex_math_f_15,
+                       complex_math_f_32,
+                       15 * 2 /*Complex data has two parts*/);
+
+ARR_DESC_DEFINE_SUBSET(complex_math_f_2,
+                       complex_math_f_32,
+                       2 * 2 /*Complex data has two parts*/);
+
+ARR_DESC_DEFINE(float32_t,
+                complex_math_zeros,
+                32 * 2 /*Complex data has two parts*/,
+                CURLY(0));
+
+/* Aggregate all float datasets */
+ARR_DESC_DEFINE(ARR_DESC_t *,
+                complex_math_f_all,
+                4,
+                CURLY(
+                      &complex_math_zeros,
+                      &complex_math_f_2,
+                      &complex_math_f_15,
+                      &complex_math_f_32
+                      ));

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c

+#include "jtest.h"
+#include "complex_math_tests.h"
+
+JTEST_DEFINE_GROUP(complex_math_tests)
+{
+    JTEST_GROUP_CALL(cmplx_conj_tests);
+    JTEST_GROUP_CALL(cmplx_dot_prod_tests);
+    JTEST_GROUP_CALL(cmplx_mag_tests);
+    JTEST_GROUP_CALL(cmplx_mag_squared_tests);
+    JTEST_GROUP_CALL(cmplx_mult_cmplx_tests);
+    JTEST_GROUP_CALL(cmplx_mult_real_tests);
+    
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c

+#include "controller_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+float32_t controller_output_fut[CONTROLLER_MAX_LEN] = {0};
+float32_t controller_output_ref[CONTROLLER_MAX_LEN] = {0};
+float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN] = {0};
+float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN] = {0};
+
+const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN] =
+{
+		0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB, 0x41F6F6A,
+		0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8, 0x3D060524, 0x93D5E570,
+		0x97D7791D, 0xFFE0C38C, 0x26749841, 0xC0A6EE54, 0x218EC386, 0x39FF3726,
+		0x8DC1F7CA, 0x702F2CF5, 0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49,
+		0x3805DE7E, 0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF,
+		0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24, 0x6CE00F5C,
+		0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530, 0x73394127, 0x773FA6F4,
+		0x9805A980, 0x838DE587, 0x9CF597F4, 0xA2AD1691, 0xFA81A473, 0x7CDC7D7F,
+		0x4A5190D0, 0xED895BB9, 0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516,
+		0x2501A3E1, 0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E,
+		0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4, 0x24DB166C,
+		0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6, 0x419E0C75, 0x46BE9F38,
+		0x2432B9B2, 0x758D83E0, 0xDCE12926, 0x3F57CB74, 0x1F4458E2, 0xF1DD639,
+		0x83A1FB49, 0x173AFC76, 0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549,
+		0x5C314C9, 0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715,
+		0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F, 0x20BFDEB4,
+		0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE, 0x9858E3E1, 0xA36A9C4E,
+		0x88BD21F9, 0xAACF7A68, 0x773665E5, 0xCEDFDF66, 0x617A9610, 0x524FC968,
+		0xC2D086CD, 0x5F008079, 0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608,
+		0xA33A2EE5, 0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5,
+		0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4, 0xB358C0D8,
+		0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF, 0x33035831, 0x13D93987,
+		0xFC542094, 0x845F317E, 0xDDC4BF8B, 0x1379E50C, 0x5C20193F, 0xFDD58298,
+		0x9D482B82, 0x4A6BE062, 0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882,
+		0xE6F8EA35, 0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD,
+		0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677, 0xFB2E04F2,
+		0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8, 0x1A8C7F28, 0x861E452E,
+		0x932D3F78, 0x7652D852, 0x73357BBA, 0xEBBB0A58, 0x62536AFA, 0x3F6B65EF,
+		0x6DC57B58, 0x9EB798CE, 0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302,
+		0xA9FD3E40, 0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3,
+		0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896, 0x6443A0FE,
+		0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820, 0xF18F0810, 0xE1548689,
+		0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B, 0xEA0C1BE0, 0xA1B785DB, 0x7086465D,
+		0x1CC10929, 0x1E1D716E, 0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4,
+		0x441F1E8B, 0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137,
+		0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615, 0x92593380,
+		0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7, 0x10E916B6, 0xE3BCFA68,
+		0x2ACB80BB, 0xE51C5590, 0x994714B5, 0xF30984EE, 0x59BBE1B4, 0xB4867DBC,
+		0xB91C706C, 0xBC16C218, 0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872,
+		0x4B167FD4, 0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55,
+		0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A, 0x9D2C662A,
+		0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C, 0x20306EDB, 0xE381AAE7,
+		0xA55DA748, 0x9B8B617B, 0x3E036FAD, 0x84E4C4A7, 0xD5A3F517, 0x669BA988,
+		0x98FDDE8C, 0x67BD85CE, 0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF,
+		0x205DB5C, 0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC,
+		0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693, 0xC42D12C0,
+		0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC, 0x8D874532, 0x5F5C9DD0,
+		0x5D167858, 0x8559FEA2, 0x9D821476, 0xD9654ED2, 0x594C0DC7, 0x1A87B506,
+		0x3F693200, 0x7A651AB5, 0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0,
+		0xB088C72F, 0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB,
+		0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D, 0x32581A06,
+		0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15, 0xBC79A9BC, 0xB7175917,
+		0x354E381C, 0x762AADD7, 0xF643DAC1, 0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4,
+		0xD7694875, 0x92D30822, 0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7,
+		0x58CE268, 0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1,
+		0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB, 0x8FF5534,
+		0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7, 0x419545EB, 0x993F7880,
+		0xAB246B20, 0x408AABC4, 0xCBF6EA49, 0xC0894C55, 0x4CAA6398, 0xA47856E9,
+		0xAF2AE47D, 0x22F55D33, 0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8,
+		0x9A77D48, 0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A,
+		0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071, 0x7F9930D4,
+		0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A, 0x144B2C12, 0x98E425C7,
+		0xBAA4B373, 0x18F0D03C, 0x99462AC0, 0xD8B4D2EF, 0x72473895, 0xA6BF5435,
+		0xEDAD53B, 0xE0912FA6, 0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929,
+		0xB89962F9, 0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0,
+		0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841, 0x73A60174,
+		0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095, 0x2B370837, 0x83DF6CE3,
+		0xDD08EEFA, 0x3F52A7C2, 0x191B4785, 0x60843D82, 0xB0DE11F1, 0x105EA26C,
+		0x6E1C7AA2, 0x47AADD14, 0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC,
+		0x744206A, 0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9,
+		0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F, 0x2E53E6C1,
+		0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5, 0x119725CC, 0x5406D347,
+		0x1B6FFAF1, 0xECCF71F1, 0x981117F2, 0x7167CA76, 0x74F4B880, 0x77A55F47,
+		0x59EADB62, 0x4A331D95, 0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1,
+		0x60D47AD5, 0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3,
+		0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E, 0x31109C58,
+		0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF, 0xBAF8D31E, 0xA4B31611,
+		0xED37F331, 0x7A832A22, 0xA22591C7, 0x722D1F89, 0x3B19CF18, 0x261B8A4D,
+		0xC3F6F6DB, 0xCF8CED61, 0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4,
+		0x3674E663, 0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD,
+		0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91, 0x4BF0C248,
+		0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26, 0x6C3B7B71, 0xD744B3ED,
+		0xFA25D2F6, 0x4CDE642D, 0xD65B8142, 0xA6F9207F, 0xE7A207BE, 0xDB506684,
+		0x44DA4780, 0x9175EA0C, 0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2,
+		0x5423D9C8, 0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1,
+		0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5, 0x1672BA91,
+		0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4, 0x32AFD40C, 0x99A5FB3B,
+		0xDD1D73A3, 0xA342CB3E, 0xA78445F5, 0x53979C3B, 0x427D7943, 0x5221B58C,
+		0xA6CE9A5E, 0xFB50ECA4, 0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04,
+		0xFBB65E0C, 0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920,
+		0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641, 0x4D6B1760,
+		0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF, 0x4E5F9493, 0x4C215DA5,
+		0x33A052B, 0x1A4D80C2, 0x40AEEBCA, 0x390D106B, 0xE9E8E018, 0x5AF3D6CF,
+		0xE35E1D4, 0xC4FB1C6, 0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6,
+		0x2227567D, 0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6,
+		0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1, 0xC9D06CBC,
+		0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47, 0x9D4804EA, 0x57DD9E67,
+		0xF89C7895, 0xF5336111, 0x25C122C8, 0x62742114, 0xCFBF6D26, 0xBF9F6482,
+		0xE6F02CD9, 0x11083202, 0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1,
+		0x3BF4DC25, 0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129,
+		0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA, 0x31C5A0AF,
+		0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98, 0x82C34882, 0x5D041F11,
+		0x8C613C57, 0xD398CFD1, 0x426F38AD, 0x5599AB1D, 0xFAFA078D, 0xAB25B413,
+		0xD94B32CF, 0xB288FE38, 0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D,
+		0x2174EBBE, 0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6,
+		0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02, 0xC20D47A4,
+		0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4, 0xC58612F4, 0xA2827F6F,
+		0xC49DCDBA, 0x679B7362, 0x4E495845, 0xCFD2F0D1, 0x395E76A0, 0x375A655E,
+		0x92E2058F, 0x73F9F0CA, 0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B,
+		0xA219E2E8, 0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF,
+		0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40, 0x157F6DDF,
+		0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58, 0xB2945F75, 0x4FA23A0E,
+		0x836EB8C0, 0xB3B18FD, 0x86114337, 0x24668ACB, 0x99BB82F0, 0x924C8A47,
+		0xBA959701, 0x81155ABF, 0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7,
+		0x7FC2802D, 0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719,
+		0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD, 0xEBA775AE,
+		0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D, 0xBBD34AB7, 0x2F85B12A,
+		0x16C5C2AD, 0x3990985D, 0x88DF3351, 0x82811AA5, 0x6D351F41, 0x4066A69D,
+		0x86B660BF, 0x6EDB4768, 0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687,
+		0x947CC9C9, 0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB,
+		0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B, 0xB7629C93,
+		0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66, 0xEC71B78C, 0xEAF4BB3A,
+		0x7C16225E, 0x668F337, 0xCBEE1608, 0x6D5B5552, 0x345DC590, 0x681209CC,
+		0x7B24A819, 0xD08A1416, 0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678,
+		0x20EECA0, 0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D,
+		0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960, 0x7CDF59F3,
+		0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110, 0xB8FCF3E3, 0xDEA059B2,
+		0x8229B6EA, 0x316486F6, 0x43919185, 0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9,
+		0x5CD41244, 0x2C9F0A7B, 0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0,
+		0xF105C20D, 0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763,
+		0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53, 0x2D2A85F6,
+		0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B, 0x9FC5AC5F, 0x11AE5DD7,
+		0xA0B9A5A9, 0xFC648AF4, 0x740009AC, 0xED0E0321, 0xB8E6A61, 0x8910C544,
+		0xC74F26C8, 0x9525CCF3, 0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D,
+		0xE1976DD4, 0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1,
+		0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB, 0xF5288568,
+		0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A, 0x1BC03B9, 0xB6BC3061,
+		0xBF30596E, 0xBE2AD27B, 0x8AC04220, 0x641979A3, 0x9ECCBB89, 0xA144FBC1,
+		0x4E8FAE26, 0x8C5A9D90, 0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D,
+		0xCEE81CDF, 0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA,
+		0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38, 0x2E77F2D,
+		0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017, 0x2D6B69A7, 0xFEDB63F9,
+		0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8, 0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6,
+		0xED193443, 0x7615EF1B, 0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022,
+		0x556E825C, 0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF,
+		0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC, 0x1E6A1101,
+		0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599, 0x54EB4809, 0x7839BE6D,
+		0xD50017DD, 0x39B1A0E1, 0x288D52D3, 0x2D52668C, 0x20D22A68, 0x4E1207D1,
+		0x3FCC0EFE, 0x47F3FE64, 0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8,
+		0x6BEAA655, 0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9,
+		0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B, 0x4DCD4EDB,
+		0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6, 0x502F41B0, 0x3616D3F1,
+		0x2E5B8E31, 0x2026EB19, 0x57E783D7, 0x467BBE00, 0x4703ABA3, 0x1F776B9C,
+		0xE2570A84, 0xFEC7DB48, 0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6,
+		0x99D5D8ED, 0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F,
+		0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB, 0x56186AA1,
+		0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94, 0xAC18B207, 0x5FC78B3,
+		0x7F10621E, 0xA769E6B2, 0xEC9F4A11, 0xCE3F982C, 0x62BA2EF5, 0xA5F239CD,
+		0x73D63FED, 0xE36E9F5E, 0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1,
+		0xCD476E86, 0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7,
+		0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78, 0xCC4BE4F6,
+		0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2, 0x55A8F5EC, 0xE81A9A75,
+		0x30A67E1B, 0x4A4A7D0C, 0x20F7F993, 0x1891805, 0x738976AD, 0xD426E7D6,
+		0x3C5CEEBF, 0x4499187F, 0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456,
+		0x421BCF29, 0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE,
+		0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46, 0x5D146234,
+		0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA, 0xB65530CC, 0x2DFAC48C,
+		0x1663D16F, 0x59B80AA, 0x950274EA, 0x92532D4A, 0x3CEF802D, 0x492FBDA5,
+		0xA63A2574, 0xEF8005C2, 0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646,
+		0xD2598516, 0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75,
+		0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F
+};
+
+/* The source data is random across the q31_t range. Accessing it by word should
+   remain random. */
+const q15_t * controller_q15_inputs = (q15_t *) controller_q31_inputs;
+
+const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN] =
+{
+		43.0264275639 , -17.0525215570 , -94.8488973910 , -8.1924989580  ,
+		7.2830326091   , 66.8368719314  , 33.9778190671  , 117.8652289772 ,
+		-129.6077797465, -14.6420815368 , 18.0239223278  , 20.6760530292  ,
+		55.0375037651  , 1.8674609862   , -85.6534302408 , -33.5750364909 ,
+		29.2110949614  , 110.4727049460 , -94.1914619387 , -1.4084169343  ,
+		83.5181653041  , 47.3073514127  , -13.3420621181 , 30.3389699104  ,
+		12.1188124277  , 100.9730921941 , -114.0146362390, -77.5823200409 ,
+		37.2019034618  , 40.0026301128  , -58.3387276630 , -34.9472398600 ,
+		-5.1169678311  , -87.7660091118 , -150.5888601131, 56.0349370503  ,
+		50.2168884079  , -74.2313236767 , 22.3648603560  , -6.8676387051  ,
+		74.8957303680  , -90.1292012823 , -55.1436241586 , -66.6732976100 ,
+		-6.7918147615  , 7.7612697081   , 35.7892605979  , -20.0470508830 ,
+		41.8369017546  , -143.7378056984, -41.9127158600 , -108.3531841158,
+		-57.1917422289 , -124.2808828105, 38.9316388820  , -77.9212517405 ,
+		37.1990818377  , -28.9545952748 , -155.6371057564, 45.8088886393  ,
+		36.2537018275  , -6.5727656016  , -104.2070491921, 45.5583813729  ,
+		-19.7674717059 , -80.4802190947 , -1.4444563441  , -42.2142256438 ,
+		36.6546339194  , -57.0866498590 , 44.4677067511  , 65.7285753407  ,
+		-103.8158864647, 25.4348723711  , -153.5419639389, 39.3608409474  ,
+		49.1658103436  , 79.5570602275  , 75.2944095996  , 58.9394700746  ,
+		-53.1018534392 , 33.4172444014  , 35.6224682287  , -64.4353396418 ,
+		-125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 ,
+		-17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604  ,
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+		-61.6528147860 , -5.9782002429  , 61.4730771294  , 43.5582379527  ,
+		55.6862408270  , 87.8745651631  , 46.3401042715  , -19.8780979663 ,
+		74.1272633369  , 29.8590452377  , -12.8665765140 , 34.2931401219  ,
+		53.9279617551  , -16.9017895140 , -70.1527553166 , -79.6367897992 ,
+		109.3728271017 , -129.2214826835, -53.4644539730 , -51.5654458993 ,
+		17.6062148433  , 3.5090251835   , 74.2615941204  , -109.3431097845,
+		40.1403465151  , 28.8714561280  , 94.0868659302  , -19.0047033845 ,
+		-60.0967410050 , -19.0998457619 , -67.2027075128 , 72.0711434846  ,
+		-17.8737851232 , 123.7050551274 , 132.6331504104 , 25.5018761009  ,
+		-36.7817189239 , -29.1580893235 , -6.5848563828  , 90.2868948516  ,
+		-35.7017258498 , -68.5675432955 , -52.4888589786 , 47.1377730021  ,
+		-7.4546621940  , -52.0657517138 , -49.0404829633 , -114.6910280126,
+		-117.6819819437, -32.7856729408 , 31.8232065591  , 12.1192973039  ,
+		35.2678513420  , -1.0336778293  , 30.7021249679  , 127.0442906046 ,
+		-84.8457819393 , 28.9862843096  , -47.3524701726 , -126.1094998460,
+		-2.9700276582  , -2.4956545870  , -53.8624121141 , -85.2114117637 ,
+		76.9057985618  , 137.1205201755 , -19.0830817212 , 14.3407526579  ,
+		-56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090,
+		0.3487447576   , 33.4499716730  , 34.7126257844  , -9.3307383323  ,
+		27.2996276947  , 10.8765676134  , -91.1032360444 , -90.9584216222 ,
+		1.6981490570   , 96.8557438791  , 56.7726390913  , -44.3246449237 ,
+		52.3260643361  , 21.5551140465  , 27.4535327381  , 2.0072717479   ,
+		7.4823125629   , 77.1185863870  , 16.1372262663  , -10.7206012957
+};
+
+const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN] =
+{
+	/* S->Kp, S->Ki, S->Kd; */
+	0.0000000000  , -1.0336778293 , 56.7726390913 ,
+	0.3487447576  , 0.0000000000  , 27.4535327381 ,
+	-29.1580893235, 1.6981490570  , 0.0000000000  ,
+	0.0000000000  , 0.0000000000  , -2.4956545870 ,
+	0.0000000000  , 8.7065613044  , 0.0000000000  ,
+	0.0000000000  , 0.0000000000  , 0.0000000000  ,
+	18.1550954005 , -5.9782002429 , 2.0072717479  ,
+	33.1212995259 , -82.1480936443, -10.5479715135,
+	-23.6296332202, 49.1171161163 , 53.1636857935 ,
+	7.2830326091  , 66.8368719314 , 33.9778190671 ,
+	9.4452708243  , 5.3300080251  , 39.0483916714 ,
+	6.9915412654  , -8.9909197429 , -78.9165936808
+};
+
+const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN] =
+{
+	0x00000000,	0xFEF760E4,	0x38C5CBAD,
+	0x00594756,	0x00000000,	0x1B741AB9,
+	0xE2D78775,	0x01B2B9E6,	0x00000000,
+	0x00000000,	0x00000000,	0xFD811CC8,
+	0x00000000,	0x08B4E134,	0x00000000,
+	0x00000000,	0x00000000,	0x00000000,
+	0x1227B455,	0xFA0594AB,	0x0201DC90,
+	0x211F0D7C,	0xADDA1689,	0xF573B824,
+	0xE85ED05B,	0x311DFB52,	0x3529E750,
+	0x074874D3,	0x42D63D3D,	0x21FA525A,
+	0x0971FD45,	0x05547B68,	0x270C6366,
+	0x06FDD5A6,	0xF7025315,	0xB1155A1E
+};
+
+
+const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN] =
+{
+	0x0000,	0xFEF7,	0x38C6,
+	0x0059,	0x0000,	0x1B74,
+	0xE2D8,	0x01B3,	0x0000,
+	0x0000,	0x0000,	0xFD81,
+	0x0000,	0x08B5,	0x0000,
+	0x0000,	0x0000,	0x0000,
+	0x1228,	0xFA06,	0x0202,
+	0x211F,	0xADDA,	0xF574,
+	0xE85F,	0x311E,	0x352A,
+	0x0748,	0x42D6,	0x21FA,
+	0x0972,	0x0554,	0x270C,
+	0x06FE,	0xF702,	0xB115
+};

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c

+#include "jtest.h"
+#include "controller_tests.h"
+
+JTEST_DEFINE_GROUP(controller_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_GROUP_CALL(pid_reset_tests);
+    JTEST_GROUP_CALL(pid_tests);
+    JTEST_GROUP_CALL(sin_cos_tests);
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c

+#include "jtest.h"
+#include "arr_desc.h"
+#include "arm_math.h"
+#include "type_abbrev.h"
+#include "test_templates.h"
+
+/* Bucket of zeros. For comparison with the output of arm_pid_reset_xxx. */
+ARR_DESC_DEFINE(float32_t, zeroes, 3, CURLY(0));
+
+/**
+ *  Define a JTEST_TEST_t for the function arm_pid_reset_xxx function having
+ *  suffix.
+ */
+#define ARM_PID_RESET_TEST(suffix)                                      \
+    JTEST_DEFINE_TEST(arm_pid_reset_##suffix##_test,                    \
+                      arm_pid_reset_##suffix)                           \
+    {                                                                   \
+        /* Initialise the pid_instance */                               \
+        arm_pid_instance_##suffix pid_inst = { 0 };                     \
+            pid_inst.state[0] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff;  \
+            pid_inst.state[1] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff;  \
+            pid_inst.state[2] = (TYPE_FROM_ABBREV(suffix)) 0xffffffff;  \
+                                                                        \
+            /* Display cycle count and run test */                      \
+            JTEST_COUNT_CYCLES(arm_pid_reset_##suffix(&pid_inst));      \
+                                                                        \
+            /* Test correctness */                                      \
+            TEST_ASSERT_BUFFERS_EQUAL(                                  \
+                pid_inst.state,                                         \
+                zeroes.data_ptr,                                        \
+                3 * sizeof(TYPE_FROM_ABBREV(suffix)));                  \
+                                                                        \
+            return JTEST_TEST_PASSED;                                   \
+    }
+
+ARM_PID_RESET_TEST(f32);
+ARM_PID_RESET_TEST(q31);
+ARM_PID_RESET_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(pid_reset_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_pid_reset_f32_test);
+    JTEST_TEST_CALL(arm_pid_reset_q31_test);
+    JTEST_TEST_CALL(arm_pid_reset_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c

+#include "jtest.h"
+#include "arr_desc.h"
+#include "arm_math.h"
+#include "ref.h"
+#include "type_abbrev.h"
+#include "test_templates.h"
+#include "controller_test_data.h"
+#include "controller_templates.h"
+
+/**
+ *  Define a JTEST_TEST_t for the function arm_pid_xxx function having
+ *  suffix.
+ */
+#define ARM_PID_TEST(suffix,type)                                       \
+    JTEST_DEFINE_TEST(arm_pid_##suffix##_test, arm_pid_##suffix)        \
+    {                                                                   \
+            uint32_t i,j;                                               \
+                                                                        \
+            arm_pid_instance_##suffix fut_pid_inst = { 0 };             \
+            arm_pid_instance_##suffix ref_pid_inst = { 0 };             \
+                                                                        \
+            for(i=0;i<CONTROLLER_MAX_COEFFS_LEN/3;i++)                  \
+            {                                                           \
+                fut_pid_inst.Kp = controller_##suffix##_coeffs[i*3+0];  \
+                fut_pid_inst.Ki = controller_##suffix##_coeffs[i*3+1];  \
+                fut_pid_inst.Kd = controller_##suffix##_coeffs[i*3+2];  \
+                ref_pid_inst.Kp = controller_##suffix##_coeffs[i*3+0];  \
+                ref_pid_inst.Ki = controller_##suffix##_coeffs[i*3+1];  \
+                ref_pid_inst.Kd = controller_##suffix##_coeffs[i*3+2];  \
+                                                                        \
+                arm_pid_init_##suffix(&fut_pid_inst, 1);                \
+                arm_pid_init_##suffix(&ref_pid_inst, 1);                \
+                                                                        \
+                /* Display parameter values */                          \
+                JTEST_DUMP_STRF("Block Size: %d\n",                     \
+                                (int)CONTROLLER_MAX_LEN);               \
+                                                                        \
+                /* Display cycle count and run test */                  \
+                JTEST_COUNT_CYCLES(                                     \
+                    for(j=0;j<CONTROLLER_MAX_LEN;j++)                   \
+                    {                                                   \
+                       *((type*)controller_output_fut + j) =            \
+                           arm_pid_##suffix(&fut_pid_inst,              \
+                           controller_##suffix##_inputs[j]);            \
+                    });                                                 \
+                                                                        \
+                for(j=0;j<CONTROLLER_MAX_LEN;j++)                       \
+                {                                                       \
+                   *((type*)controller_output_ref + j) =                \
+                        ref_pid_##suffix(&ref_pid_inst,                 \
+                        controller_##suffix##_inputs[j]);               \
+                }                                                       \
+                                                                        \
+                /* Test correctness */                                  \
+                CONTROLLER_SNR_COMPARE_INTERFACE(                       \
+                        CONTROLLER_MAX_LEN,                             \
+                        type);                                          \
+            }                                                           \
+                                                                        \
+            return JTEST_TEST_PASSED;                                   \
+    }
+
+ARM_PID_TEST(f32,float32_t);
+ARM_PID_TEST(q31,q31_t);
+ARM_PID_TEST(q15,q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(pid_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_pid_f32_test);
+    JTEST_TEST_CALL(arm_pid_q31_test);
+    JTEST_TEST_CALL(arm_pid_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.c

+#include "jtest.h"
+#include "arr_desc.h"
+#include "arm_math.h"
+#include "ref.h"
+#include "type_abbrev.h"
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+                arm_sin_cos_degrees_f32,
+                9,
+                CURLY(
+                    0,
+                    17,
+                    45,
+                    90,
+                    180,
+                    360,
+                    362,
+                    -73,
+                    -191.111
+                      ));
+
+/* The Q31 version of the function maps numbers in the range [-1, 0.9999999]
+ * to degrees in the range [-180, 179]*/
+ARR_DESC_DEFINE(q31_t,
+                arm_sin_cos_degrees_q31,
+                6,
+                CURLY(
+                    0,
+                    0x80000000, /* -1 */
+                    0x7fffffff, /* 0.99999 */
+                    /* Randoms */
+                    0xf7badafa,
+                    0x285954a1,
+                    0xb9d09511
+                      ));
+
+/*--------------------------------------------------------------------------------*/
+/* Output Variables */
+/*--------------------------------------------------------------------------------*/
+float32_t sin_val_fut = 0;
+float32_t cos_val_fut = 0;
+float32_t sin_val_ref = 0;
+float32_t cos_val_ref = 0;
+
+/*--------------------------------------------------------------------------------*/
+/* Test Definitions */
+/*--------------------------------------------------------------------------------*/
+
+#define MAX_DELTA_f32 50.0e-8f
+#define ABS(x) ((x) > 0 ? (x) : -(x))
+
+/*
+  Function to test correctness of sin_cos output by comparing it with reference library
+*/
+#define COMPARISON_INTERFACE(type, threshold)                           \
+    if ( (ABS((type) sin_val_ref - (type) sin_val_fut) >                 \
+         (type) threshold ) ||                                          \
+        (ABS((type) cos_val_ref - (type) cos_val_fut) >                 \
+         (type) threshold))                                             \
+    {                                                                   \
+        JTEST_DUMP_STRF("Error: %f %f\n",                               \
+                        ABS((type) sin_val_ref - (type) sin_val_fut),   \
+                        ABS((type) cos_val_ref - (type) cos_val_fut));  \
+        return JTEST_TEST_FAILED;                                       \
+    }
+
+/*
+  Sine and cosine test function for float32_t input
+*/
+JTEST_DEFINE_TEST(arm_sin_cos_f32_test, arm_sin_cos_f32)
+{
+    /* Test function for all input degree values */
+    TEMPLATE_DO_ARR_DESC(
+        degree_idx, TYPE_FROM_ABBREV(f32),
+        degree, arm_sin_cos_degrees_f32
+        ,
+        /* Display cycle count and run test */
+        JTEST_COUNT_CYCLES(
+            arm_sin_cos_f32(
+                degree,
+                (TYPE_FROM_ABBREV(f32) *) &sin_val_fut,
+                (TYPE_FROM_ABBREV(f32) *) &cos_val_fut)
+        );
+        ref_sin_cos_f32(
+            degree,
+            (TYPE_FROM_ABBREV(f32) *) &sin_val_ref,
+            (TYPE_FROM_ABBREV(f32) *) &cos_val_ref);
+
+        /* Test correctness */
+        COMPARISON_INTERFACE(
+            TYPE_FROM_ABBREV(f32),
+            MAX_DELTA_f32));
+
+    return JTEST_TEST_PASSED;
+}
+
+
+/*
+  Sine and cosine test function for q31_t input
+*/
+JTEST_DEFINE_TEST(arm_sin_cos_q31_test,
+                  arm_sin_cos_q31)
+{
+    /* Test function for all input degree values */
+    TEMPLATE_DO_ARR_DESC(
+        degree_idx, TYPE_FROM_ABBREV(q31),
+        degree, arm_sin_cos_degrees_q31
+        ,
+        /* Display cycle count and run test */
+        JTEST_COUNT_CYCLES(
+            arm_sin_cos_q31(
+                degree,
+                (TYPE_FROM_ABBREV(q31) *) &sin_val_fut,
+                (TYPE_FROM_ABBREV(q31) *) &cos_val_fut)
+        );
+        ref_sin_cos_q31(
+            degree,
+            (TYPE_FROM_ABBREV(q31) *) &sin_val_ref,
+            (TYPE_FROM_ABBREV(q31) *) &cos_val_ref);
+
+        /* Convert q31 numbers to float for comparison purposes. */
+        ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &sin_val_fut, &sin_val_fut, 1);
+        ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &cos_val_fut, &cos_val_fut, 1);
+        ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &sin_val_ref, &sin_val_ref, 1);
+        ref_q31_t_to_float((TYPE_FROM_ABBREV(q31) *) &cos_val_ref, &cos_val_ref, 1);
+
+        /* Test correctness */
+        COMPARISON_INTERFACE(
+            TYPE_FROM_ABBREV(f32),
+            MAX_DELTA_f32));
+
+    return JTEST_TEST_PASSED;
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(sin_cos_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_sin_cos_f32_test);
+    JTEST_TEST_CALL(arm_sin_cos_q31_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c

+#include "jtest.h"
+#include "ref.h"
+#include "arr_desc.h"
+#include "fast_math_templates.h"
+#include "fast_math_test_data.h"
+#include "type_abbrev.h"
+
+SQRT_TEST_TEMPLATE_ELT1(q31);
+SQRT_TEST_TEMPLATE_ELT1(q15);
+
+SIN_COS_TEST_TEMPLATE_ELT1(f32, float32_t, sin);
+SIN_COS_TEST_TEMPLATE_ELT1(q31, q31_t, sin);
+SIN_COS_TEST_TEMPLATE_ELT1(q15, q15_t, sin);
+
+SIN_COS_TEST_TEMPLATE_ELT1(f32, float32_t, cos);
+SIN_COS_TEST_TEMPLATE_ELT1(q31, q31_t, cos);
+SIN_COS_TEST_TEMPLATE_ELT1(q15, q15_t, cos);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(fast_math_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_sqrt_q31_test);
+    JTEST_TEST_CALL(arm_sqrt_q15_test);
+
+    JTEST_TEST_CALL(arm_sin_f32_test);
+    JTEST_TEST_CALL(arm_sin_q31_test);
+    JTEST_TEST_CALL(arm_sin_q15_test);
+
+    JTEST_TEST_CALL(arm_cos_f32_test);
+    JTEST_TEST_CALL(arm_cos_q31_test);
+    JTEST_TEST_CALL(arm_cos_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c

+#include "fast_math_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+float32_t fast_math_output_fut[FAST_MATH_MAX_LEN] = {0};
+float32_t fast_math_output_ref[FAST_MATH_MAX_LEN] = {0};
+float32_t fast_math_output_f32_fut[FAST_MATH_MAX_LEN] = {0};
+float32_t fast_math_output_f32_ref[FAST_MATH_MAX_LEN] = {0};
+
+const q31_t fast_math_q31_inputs[FAST_MATH_MAX_LEN] =
+{
+    0x414A5524, 0x4CAB5A17, 0x2D6F5B56, 0x7DAF4E3B, 0x29B226EB, 0x41F6F6A ,
+    0x25CE38BF, 0x3A970AFA, 0x3A44382A, 0x05540F8 , 0x3D060524, 0x13D56570,
+    0x17D7791D, 0x7FE0438C, 0x26741841, 0x40A66E54, 0x218E4386, 0x39FF3726,
+    0x0DC177CA, 0x702F2CF5, 0x41142FF1, 0x6C1476AB, 0x15F640DD, 0x662C4E49,
+    0x38055E7E, 0x770871FE, 0x4F8B5360, 0x0D1928A0, 0x57647821, 0x258558CF,
+    0x0C0C604D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0x36462E24, 0x6CE00F5C,
+    0x66D40948, 0x355B5831, 0x3B72150A, 0x1EB61530, 0x73394127, 0x773F26F4,
+    0x18052980, 0x038D6587, 0x1CF517F4, 0x22AD1691, 0x7A812473, 0x7CDC7D7F,
+    0x4A5110D0, 0x6D895BB9, 0x0FD60F35, 0x1A215530, 0x20EB6DDA, 0x3DE62516,
+    0x250123E1, 0x5ED813C8, 0x61E175B1, 0x2CBB32F3, 0x6D350907, 0x5B140D7E,
+    0x6EAE272D, 0x3E221841, 0x418B7B88, 0x26BB1B80, 0x3CF010E4, 0x24DB166C,
+    0x79AB7E42, 0x62DF28D1, 0x47004665, 0x63F56FC6, 0x419E0C75, 0x46BE1F38,
+    0x243239B2, 0x758D03E0, 0x5CE12926, 0x3F574B74, 0x1F4458E2, 0x71D5639 ,
+    0x03A17B49, 0x173A7C76, 0x06EF7531, 0x48D32F34, 0x7D3E3063, 0x0F2F3549,
+    0x5C314C9 , 0x18CB6B6D, 0x26F83697, 0x447B1E9C, 0x2E323A33, 0x50745715,
+    0x01AC5746, 0x655A4E04, 0x4891060F, 0x1DA36B4F, 0x60E6227F, 0x20BF5EB4,
+    0x50B3225B, 0x40C10544, 0x415656C , 0x15405EAE, 0x185863E1, 0x236A1C4E,
+    0x08BD21F9, 0x2ACF7A68, 0x773665E5, 0x4EDF5F66, 0x617A1610, 0x524F4968,
+    0x42D006CD, 0x5F000079, 0x24DC2447, 0x6A4F5599, 0x37064D4A, 0x1DE70608,
+    0x233A2EE5, 0x137E488E, 0x18061B7B, 0x4079569D, 0x24A817D5, 0x44CE48F5,
+    0x575F7883, 0x22406802, 0x71AD70BB, 0x1D4A5D79, 0x3CBC7CE4, 0x335840D8,
+    0x05792E47, 0x27AD2C05, 0x3D196EAB, 0x331A40AF, 0x33035831, 0x13D93987,
+    0x7C542094, 0x045F317E, 0x5DC43F8B, 0x1379650C, 0x5C20193F, 0x7DD50298,
+    0x1D482B82, 0x4A6B6062, 0x5C8A757B, 0x272917C1, 0x10E16FBC, 0x355A5882,
+    0x66F86A35, 0x604555A1, 0x7DF7FBB , 0x758A6216, 0x1A113463, 0x53541BAD,
+    0x21576756, 0x483B6D8D, 0x1F052FCC, 0x4EA63DFB, 0x55B84677, 0x7B2E04F2,
+    0x787A796C, 0x04A12CD3, 0x46029BD , 0x1DB22DD8, 0x1A8C7F28, 0x061E452E,
+    0x132D3F78, 0x76525852, 0x73357BBA, 0x6BBB0A58, 0x62536AFA, 0x3F6B65EF,
+    0x6DC57B58, 0x1EB718CE, 0x66B02740, 0x5FF60B47, 0x32477B8F, 0x7FF35302,
+    0x29FD3E40, 0x475A43D1, 0x6FF9528A, 0x2018209D, 0x47E079C9, 0x4CF576D3,
+    0x28074E34, 0x5D6F58ED, 0x234045D1, 0x51CE35F9, 0x25297896, 0x644320FE,
+    0x0F4449A9, 0x54C361C6, 0x701D52F1, 0x4E094820, 0x718F0810, 0x61540689,
+    0x79DE5A1F, 0x52865C23, 0x48AC3A4B, 0x6A0C1BE0, 0x21B705DB, 0x7086465D,
+    0x1CC10929, 0x1E1D716E, 0x6D231D4C, 0x20495108, 0x38FF1971, 0x149C78D4,
+    0x441F1E8B, 0x43D95372, 0x69C324B4, 0x210B7DC9, 0x47815E78, 0x02476137,
+    0x6163DDF , 0x390D6EC2, 0x2F684E5B, 0x0E680ABD, 0x02232615, 0x12593380,
+    0x7B1465FE, 0x065A6957, 0x130F53EB, 0x6D772EF7, 0x10E916B6, 0x63BC7A68,
+    0x2ACB00BB, 0x651C5590, 0x194714B5, 0x730904EE, 0x59BB61B4, 0x34867DBC,
+    0x391C706C, 0x3C164218, 0x28931CD0, 0x129A66AB, 0x13171F4D, 0x62882872,
+    0x4B167FD4, 0x66902F4C, 0x7A794932, 0x54B152C , 0x30856EA9, 0x39466D55,
+    0x36696451, 0x0F5B1E8C, 0x077A3C6A, 0x51B956B4, 0x367E2D2A, 0x1D2C662A,
+    0x78FB6880, 0x4E6D40B6, 0x40706FDC, 0x4DF9679C, 0x20306EDB, 0x63812AE7,
+    0x255D2748, 0x1B8B617B, 0x3E036FAD, 0x04E444A7, 0x55A37517, 0x669B2988,
+    0x18FD5E8C, 0x67BD05CE, 0x34BB346C, 0x76994800, 0x05B958B6, 0x6DFA2FEF,
+    0x2055B5C , 0x1F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB90B61, 0x43235DAC,
+    0x31D424B4, 0x768C0D7E, 0x162F2F9D, 0x7B2A7A99, 0x79392693, 0x442D12C0,
+    0x0692273E, 0x59A16E80, 0x5D956856, 0x44E73DAC, 0x0D874532, 0x5F5C1DD0,
+    0x5D167858, 0x05597EA2, 0x1D821476, 0x59654ED2, 0x594C0DC7, 0x1A873506,
+    0x3F693200, 0x7A651AB5, 0x20CC3C8A, 0x1F9E662C, 0x78E7631 , 0x2A01DA0 ,
+    0x3088472F, 0x12EE0D42, 0x360D4D5F, 0x73337E48, 0x0D634C06, 0x233A0ACB,
+    0x706651ED, 0x7AA54079, 0x262239D1, 0x3EBB6BB6, 0x225A4F3D, 0x32581A06,
+    0x6E6F5780, 0x577377C7, 0x75ED1DDC, 0x10DF2D15, 0x3C7929BC, 0x37175917,
+    0x354E381C, 0x762A2DD7, 0x76435AC1, 0x73BB749E, 0x52FE4E7E, 0x6C8140F4,
+    0x57694875, 0x12D30822, 0x474227CF, 0x37926D98, 0x121C7E24, 0x204E1EE7,
+    0x58C6268 , 0x2152080 , 0x316C3323, 0x7AB14A31, 0x61C13C03, 0x7D8E74F1,
+    0x73F446D0, 0x6C6C6A0A, 0x3BFD79FB, 0x67242969, 0x3E5524EB, 0x0FF5534 ,
+    0x52F05F1C, 0x17102DE3, 0x540F4A21, 0x798468E7, 0x419545EB, 0x193F7880,
+    0x2B246B20, 0x408A2BC4, 0x4BF66A49, 0x40894C55, 0x4CAA6398, 0x247856E9,
+    0x2F2A647D, 0x22F55D33, 0x70D37915, 0x50634C72, 0x5983671 , 0x2BCC5AF8,
+    0x1A77D48 , 0x411B5CFA, 0x71074D7E, 0x3A6B3593, 0x61425F05, 0x6271012A,
+    0x5B830310, 0x3D8418CA, 0x10A50792, 0x239F7137, 0x213D5071, 0x7F9930D4,
+    0x2462664F, 0x54180F8E, 0x291505BA, 0x6586387A, 0x144B2C12, 0x18E425C7,
+    0x3AA43373, 0x18F0503C, 0x19462AC0, 0x58B452EF, 0x72473895, 0x26BF5435,
+    0x6DA553B , 0x60912FA6, 0x5C337331, 0x3D93CD7 , 0x4D035752, 0x20691929,
+    0x389962F9, 0x36E701E9, 0x758B642C, 0x5FCA69E3, 0x596027F4, 0x2D5A2FD0,
+    0x5F18324A, 0x3DB165AA, 0x76BA3876, 0x1BC21AF6, 0x3CC10841, 0x73A60174,
+    0x625B7F58, 0x67C57724, 0x4458653C, 0x61573095, 0x2B370837, 0x03DF6CE3,
+    0x5D086EFA, 0x3F5227C2, 0x191B4785, 0x60843D82, 0x30DE11F1, 0x105E226C,
+    0x6E1C7AA2, 0x47AA5D14, 0x36676D03, 0x3B8D4DF6, 0x7372694 , 0x409521DC,
+    0x744206A , 0x4722023F, 0x2BE46AD5, 0x63E11D76, 0x4A4A09AB, 0x5CF252B9,
+    0x31586916, 0x4DFD7D84, 0x32037634, 0x2D7329D4, 0x4524582F, 0x2E5366C1,
+    0x3B0E019B, 0x38530C6A, 0x6A2542D , 0x0A6A00E5, 0x119725CC, 0x54065347,
+    0x1B6F7AF1, 0x6CCF71F1, 0x181117F2, 0x71674A76, 0x74F43880, 0x77A55F47,
+    0x59EA5B62, 0x4A331D95, 0x3CBB276F, 0x245C4D50, 0x4718D5  , 0x07CE05D1,
+    0x60D47AD5, 0x25CA1C40, 0x30061766, 0x669B39DF, 0x3D5F1320, 0x19306AD3,
+    0x28B30325, 0x0DD090F , 0x6A6E6F37, 0x2DF16F66, 0x2B514C7E, 0x31101C58,
+    0x7D4847FC, 0x515341CA, 0x77AB0EA6, 0x41320DAF, 0x3AF8531E, 0x24B31611,
+    0x6D377331, 0x7A832A22, 0x222511C7, 0x722D1F89, 0x3B194F18, 0x261B0A4D,
+    0x43F676DB, 0x4F8C6D61, 0x190F2250, 0x202E72A9, 0x560D4EA2, 0x308E67B4,
+    0x36746663, 0x17CC3852, 0x27EB2EAC, 0x7FDE0AA8, 0x264719A , 0x23261EDD,
+    0x3C0B339E, 0x06284D40, 0x48D82ECB, 0x24D44CF8, 0x43631B91, 0x4BF04248,
+    0x36497B9B, 0x68273C58, 0x630B7AF9, 0x20CC3F26, 0x6C3B7B71, 0x574433ED,
+    0x7A2552F6, 0x4CDE642D, 0x565B0142, 0x26F9207F, 0x67A207BE, 0x5B506684,
+    0x44DA4780, 0x11756A0C, 0x156104AF, 0x415561B0, 0x6E3A6886, 0x1DBA1EA2,
+    0x542359C8, 0x4C024E22, 0x758F052A, 0x1DD6395 , 0x2D194BAD, 0x616475A1,
+    0x42084602, 0x09C274AD, 0x13CB5562, 0x57FE2D5B, 0x607A4EE5, 0x16723A91,
+    0x4F624CCF, 0x2E5E24A3, 0x28FE6FAF, 0x3DDA6EF4, 0x32AF540C, 0x19A57B3B,
+    0x5D1D73A3, 0x23424B3E, 0x278445F5, 0x53971C3B, 0x427D7943, 0x5221358C,
+    0x26CE1A5E, 0x7B506CA4, 0x3B86636E, 0x60831F6D, 0x45E142F3, 0x21B77B04,
+    0x7BB65E0C, 0x78B80F5E, 0x7D8D172B, 0x3BF33A90, 0x2D572D9 , 0x2B5B4920,
+    0x36A05E01, 0x52745306, 0x47C64855, 0x1CAA669B, 0x304A2641, 0x4D6B1760,
+    0x3E176D79, 0x523241B0, 0x24A67957, 0x4BDE76AF, 0x4E5F1493, 0x4C215DA5,
+    0x33A052B , 0x1A4D00C2, 0x40AE6BCA, 0x390D106B, 0x69E86018, 0x5AF356CF,
+    0x63561D4 , 0x44F31C6 , 0x14B6299B, 0x0D2E25F0, 0x4CBF132A, 0x45AC18B6,
+    0x2227567D, 0x06B54E2F, 0x26344534, 0x22C515EC, 0x2442370D, 0x6C3721C6,
+    0x34EF687D, 0x1C06323A, 0x6AF36A60, 0x60396F52, 0x6AE70AA1, 0x49D06CBC,
+    0x6F9576C8, 0x584C4258, 0x3A9A27BB, 0x66DF0D47, 0x1D4804EA, 0x57DD1E67,
+    0x789C7895, 0x75336111, 0x25C122C8, 0x62742114, 0x4FBF6D26, 0x3F9F6482,
+    0x66F02CD9, 0x11083202, 0x499E2618, 0x7EBC1351, 0x440112F1, 0x49DF7BC1,
+    0x3BF45C25, 0x31BA7FA0, 0x61AF1AED, 0x6B1F7D29, 0x2D865294, 0x63E01129,
+    0x7E9E77A5, 0x100435D7, 0x1FE3A71 , 0x08597C81, 0x722849FA, 0x31C520AF,
+    0x7BA178DC, 0x7F102D31, 0x5CA07864, 0x150E6F98, 0x02C34882, 0x5D041F11,
+    0x0C613C57, 0x53984FD1, 0x426F38AD, 0x55992B1D, 0x7AFA078D, 0x2B253413,
+    0x594B32CF, 0x32887E38, 0x28933B46, 0x1A0B4168, 0x291B4A94, 0x653A5E8D,
+    0x21746BBE, 0x5EFE6415, 0x30DA429C, 0x50C5640C, 0x34711AA4, 0x529C67A6,
+    0x105957CD, 0x4D287499, 0x03CA0AA7, 0x28385832, 0x25A04A02, 0x420D47A4,
+    0x35627556, 0x4BC11E4C, 0x59E215C7, 0x27E838B4, 0x458612F4, 0x22827F6F,
+    0x449D4DBA, 0x679B7362, 0x4E495845, 0x4FD270D1, 0x395E76A0, 0x375A655E,
+    0x12E2058F, 0x73F970CA, 0x61EF73B3, 0x51FF5362, 0x67410345, 0x7FDA0B3B,
+    0x221962E8, 0x17AB6543, 0x26557412, 0x4B30084D, 0x268E191D, 0x7E0D13DF,
+    0x73EF127D, 0x4DEC5DB1, 0x77FA745F, 0x56002898, 0x12DD0A40, 0x157F6DDF,
+    0x42A55F8E, 0x43597924, 0x7B630C3F, 0x338B6B58, 0x32945F75, 0x4FA23A0E,
+    0x036E38C0, 0x33B18FD , 0x06114337, 0x24660ACB, 0x19BB02F0, 0x124C0A47,
+    0x3A951701, 0x01155ABF, 0x0C612D71, 0x36074CA7, 0x51660C41, 0x635F58C7,
+    0x7FC2002D, 0x0E6A7CF3, 0x65B07D07, 0x015F6A6B, 0x791B70DD, 0x6E475719,
+    0x424314C7, 0x68426EB , 0x71942FEE, 0x464A2F52, 0x677579FD, 0x6BA775AE,
+    0x1F66EFF , 0x1A795237, 0x78D9545F, 0x1D0B344D, 0x3BD34AB7, 0x2F85312A,
+    0x16C542AD, 0x3990185D, 0x08DF3351, 0x02811AA5, 0x6D351F41, 0x4066269D,
+    0x06B660BF, 0x6EDB4768, 0x5DD70CF0, 0x35D74F6E, 0x689E220C, 0x11431687,
+    0x147C49C9, 0x385762BD, 0x302F0AE4, 0x1DAB67F8, 0x483256C9, 0x37D50FCB,
+    0x4EA82711, 0x4D7B2C98, 0x19DB78BC, 0x58DE0DC2, 0x6AFF7E7B, 0x37621C93,
+    0x792C6E19, 0x77001192, 0x7F88439D, 0x2E196A66, 0x6C71378C, 0x6AF43B3A,
+    0x7C16225E, 0x6687337 , 0x4BEE1608, 0x6D5B5552, 0x345D4590, 0x681209CC,
+    0x7B242819, 0x508A1416, 0x19880FE3, 0x1FC7288A, 0x24BD0502, 0x6A1D1678,
+    0x20E6CA0 , 0x59BE2057, 0x5ADE11EB, 0x5EA8649D, 0x7A200E6F, 0x1149481D,
+    0x72281E93, 0x0A5B0451, 0x67312D58, 0x63B849F1, 0x52217960, 0x7CDF59F3,
+    0x33C775C0, 0x1EBA0799, 0x7DF1506 , 0x34E96110, 0x38FC73E3, 0x5EA059B2,
+    0x022936EA, 0x316406F6, 0x43911185, 0x6C0D10F3, 0x1C6F3DF8, 0x38DB12A9,
+    0x5CD41244, 0x2C9F0A7B, 0x5F4A315F, 0x77CE1C66, 0x4C800860, 0x318D53E0,
+    0x7105420D, 0x575361F2, 0x750810BA, 0x217E4CA5, 0x2010140 , 0x4D884763,
+    0x42BB0DA7, 0x32D53A74, 0x141C6CD4, 0x087F5FC3, 0x464B53  , 0x2D2A05F6,
+    0x15532B45, 0x5D5C3CE1, 0x3EB9216A, 0x2214611B, 0x1FC52C5F, 0x11AE5DD7,
+    0x20B925A9, 0x7C640AF4, 0x740009AC, 0x6D0E0321, 0x38E6A61 , 0x09104544,
+    0x474F26C8, 0x15254CF3, 0x341A6B59, 0x661904CE, 0x598B2197, 0x2412659D,
+    0x61976DD4, 0x329B3E16, 0x08FD1FB0, 0x304006F3, 0x3456309 , 0x55CC15F1,
+    0x59DA7630, 0x5C801335, 0x0036D52 , 0x353775A5, 0x299476EB, 0x75280568,
+    0x766F5264, 0x2EA233A6, 0x647619F3, 0x7FB30C7A, 0x1BC03B9 , 0x36BC3061,
+    0x3F30596E, 0x3E2A527B, 0x0AC04220, 0x641979A3, 0x1ECC3B89, 0x21447BC1,
+    0x4E8F2E26, 0x0C5A1D90, 0x299E5467, 0x57C947E3, 0x1D4865ED, 0x76F31C3D,
+    0x4EE81CDF, 0x3479195E, 0x6FFB3AE1, 0x5C82398 , 0x300F7364, 0x47940AFA,
+    0x3B853E3E, 0x598C440D, 0x224A3D89, 0x3A674204, 0x22880A38, 0x2E77F2D ,
+    0x22841C9C, 0x4F0609C3, 0x1FE90922, 0x09335017, 0x2D6B69A7, 0x7EDB63F9,
+    0x099A74EF, 0x1F9F1B40, 0x24BE17E8, 0x251D2F7A, 0x16AC50D3, 0x28D7ED6 ,
+    0x6D193443, 0x76156F1B, 0x30DF6A4E, 0x64FF6794, 0x63DB2C9A, 0x74353022,
+    0x556E025C, 0x23802AF9, 0x425018A4, 0x675A18BB, 0x70B227B9, 0x7FB01BF ,
+    0x63E7910 , 0x6C661591, 0x65745D2B, 0x4F6E379D, 0x52B32FAC, 0x1E6A1101,
+    0x1DE22385, 0x2338191F, 0x469704B6, 0x4BAB4599, 0x54EB4809, 0x78393E6D,
+    0x550017DD, 0x39B120E1, 0x288D52D3, 0x2D52668C, 0x20D22A68, 0x4E1207D1,
+    0x3FCC0EFE, 0x47F37E64, 0x25177A90, 0x34BF5D4D, 0x5A8D3DCE, 0x6F7275A8,
+    0x6BEA2655, 0x2A1810FC, 0x64DB593A, 0x0A4D4BC0, 0x2C402E93, 0x71C077F9,
+    0x6F0C4577, 0x70412414, 0x752F1DC1, 0x582E38EA, 0x2C455F7B, 0x4DCD4EDB,
+    0x12BC2696, 0x7B037135, 0x4FCA1F8C, 0x3D5E75F6, 0x502F41B0, 0x361653F1,
+    0x2E5B0E31, 0x20266B19, 0x57E703D7, 0x467B3E00, 0x47032BA3, 0x1F776B9C,
+    0x62570A84, 0x7EC75B48, 0x1BD5012 , 0x7D0A2D5D, 0x7FCC29F2, 0x291304B6,
+    0x19D558ED, 0x47551C8 , 0x7D12738F, 0x3ADE0892, 0x5F741997, 0x25D2E2F ,
+    0x2B9F2269, 0x5C134FED, 0x15E92399, 0x54437F4E, 0x272D32AB, 0x56186AA1,
+    0x7E4D355C, 0x234D7836, 0x2A871760, 0x4637A94 , 0x2C183207, 0x5FC78B3 ,
+    0x7F10621E, 0x276966B2, 0x6C9F4A11, 0x4E3F182C, 0x62BA2EF5, 0x25F239CD,
+    0x73D63FED, 0x636E1F5E, 0x0AC15A0E, 0x3F3D33EB, 0x738326EA, 0x35C366B1,
+    0x4D476E86, 0x02F63208, 0x711A1FC1, 0x426A4396, 0x7E4D1B93, 0x75E46DB7,
+    0x2F3C44A7, 0x51A56F5C, 0x7AD2463D, 0x0A5639CA, 0x49952C78, 0x4C4B64F6,
+    0x3AFE7F8D, 0x66993D04, 0x43867F37, 0x4BC146C2, 0x55A875EC, 0x681A1A75,
+    0x30A67E1B, 0x4A4A7D0C, 0x20F77993, 0x1891805 , 0x738976AD, 0x542667D6,
+    0x3C5C6EBF, 0x4499187F, 0x2BF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456,
+    0x421B4F29, 0x76740F9C, 0x09163B8D, 0x3D72AAB , 0x1AD54DD7, 0x754946EE,
+    0x7317342B, 0x218546D4, 0x10563DA7, 0x54BB4CCE, 0x0CE63E46, 0x5D146234,
+    0x33BE6C63, 0x325044E5, 0x09D72335, 0x07C36BA , 0x365530CC, 0x2DFA448C,
+    0x1663516F, 0x59B00AA , 0x150274EA, 0x12532D4A, 0x3CEF002D, 0x492F3DA5,
+    0x263A2574, 0x6F8005C2, 0x14A10651, 0x2F627ABA, 0x68293238, 0x26987646,
+    0x52590516, 0x10144D36, 0x59B151B9, 0x2B2A4F05, 0x53953699, 0x27851C75,
+    0x180646F3, 0x2E970306, 0x32843145, 0x18F4FE8F
+};
+
+/* The source data is random across the q31_t range. Accessing it by word should
+   remain random. */
+const q15_t * fast_math_q15_inputs = (q15_t *) fast_math_q31_inputs;
+
+const float32_t fast_math_f32_inputs[FAST_MATH_MAX_LEN] =
+{
+       -1.5E-07, 5.0545058, 6.1958757, 0.1884450, 3.3656774, 0.5471223,
+        -5.0396892, 6.2149808, 0.4206357, 5.9024140, 0.1142128, 4.2966847,
+        -4.9243615, 3.3560853, 5.5628775, 5.6486144, 3.9328821, 0.8662564,
+        -1.3684878, 1.1444261, 0.2627620, 0.6719343, 3.8732286, 5.9040643,
+        -2.2271110, 2.5800587, 6.1848498, 5.9412493, 4.2514839, 6.2096863,
+        -4.8181437, 2.1155439, 4.1618680, 1.5341357, 1.8567268, 4.2736867,
+        -3.3165594, 2.5861183, 3.7864876, 4.7156566, 3.6664471, 3.4670146,
+        -3.6666823, 3.2158594, 0.5189454, 4.5211925, 6.2590334, 2.2276047,
+        -6.1025991, 2.1768018, 5.5703194, 2.8569321, 2.5976403, 1.3680509,
+        -0.7895111, 1.9409676, 4.5622487, 4.9189303, 4.3591961, 0.0615894,
+        -5.2980657, 5.7951829, 4.8440482, 0.2680398, 2.3762136, 4.4254964,
+        -4.5836656, 1.4091744, 1.6905207, 4.2287795, 3.0001720, 3.9189258,
+        -1.4856273, 1.1129014, 5.2128031, 4.8187110, 5.8715002, 0.6778860,
+        -1.1449692, 0.6226340, 3.0772767, 1.2141962, 5.6290528, 0.6225986,
+        -0.2775005, 3.5015887, 4.8537297, 1.9599772, 1.1245801, 2.1297213,
+        -1.3203840, 3.2053828, 5.6948550, 3.9516457, 0.6379562, 2.4558128,
+        -0.3431663, 3.1496534, 2.7125841, 6.2678565, 5.0994494, 3.0514394,
+        -5.6199810, 0.8642307, 2.4504731, 5.8267510, 5.7647838, 4.4835177,
+        3.8851284, 2.1569414, 5.8812331, 0.7839784, 4.5904032, 4.0619375,
+        5.2348483, 2.5024810, 4.7112719, 5.2478452, 2.0260784, 3.4699621,
+        6.1520498, 3.4514073, 2.0761128, 3.8922546, 2.2659464, 4.7532896,
+        2.6006151, 3.0934955, 4.3652005, 6.1118673, 2.0593452, 5.2640727,
+        4.6437278, 5.9952549, 0.2005758, 2.2422740, 4.1635768, 1.7687265,
+        1.4475395, 4.4681525, 3.9243074, 3.7109036, 4.1496541, 0.2987948,
+        2.1914796, 2.8358565, 1.5136507, 4.4927603, 5.3795520, 1.7687650,
+        4.5933278, 0.8655898, 5.2572843, 0.8708603, 3.6958286, 2.3006310,
+        5.0690197, 3.1653480, 3.0762120, 5.5106597, 2.2188555, 2.8239372,
+        6.0540393, 0.2657649, 6.1132775, 1.1888217, 4.1916405, 3.6847088,
+        4.2418564, 2.2683684, 3.8973243, 5.0966113, 0.1209983, 0.5269928,
+        6.1248595, 4.0925498, 1.4529100, 2.5352096, 0.7666775, 1.6866509,
+        1.6200953, 2.0839142, 0.9565145, 2.1865966, 0.7644026, 5.5552975,
+        0.5923686, 5.8436176, 2.5071164, 0.2978322, 2.1511962, 4.6242118,
+        4.9931353, 3.4237447, 4.3116692, 5.6148598, 0.3442670, 1.9079607,
+        0.2902301, 1.2282167, 4.5249352, 4.5349096, 5.5153742, 3.6595342,
+        0.4441228, 5.7977751, 5.0288862, 1.7966571, 3.4159368, 6.1875316,
+        4.4967379, 5.2714014, 2.7222564, 2.9570223, 3.5230663, 1.6907520,
+        4.7062218, 3.1660203, 4.0640250, 1.9336225, 0.8716326, 2.9881129,
+        2.2773988, 4.9518627, 4.9027432, 4.2003861, 0.8388295, 0.1354396,
+        3.5175829, 1.8901016, 5.9024853, 6.1631993, 1.8008890, 5.0317023,
+        5.6304337, 3.7543702, 5.5544410, 5.9296402, 3.4504620, 4.5765894,
+        3.6238793, 0.1624673, 2.8056369, 4.0608350, 3.2748147, 2.3393094,
+        5.8881908, 5.2121085, 5.3349614, 2.3407017, 3.7270886, 5.4824095,
+        5.8653636, 4.2000849, 1.2992148, 4.1082644, 0.4527132, 2.5555406,
+        4.1904544, 5.8667713, 5.0953493, 3.0445066, 4.7547955, 2.6203864,
+        6.1059115, 6.2076281, 5.4295991, 2.4434288, 2.8572272, 1.5499814,
+        4.9286757, 5.5470323, 5.7410198, 3.5078076, 3.7627993, 0.9354200,
+        5.6530665, 2.8299063, 1.2922774, 5.6526739, 4.7914663, 5.5448250,
+        1.7903950, 4.2300036, 4.1737937, 0.7716694, 2.5592571, 1.7296789,
+        4.5029688, 1.7805566, 5.6309835, 5.1935484, 2.4506089, 3.1284165,
+        4.3655898, 5.2424950, 3.8304163, 3.6111801, 2.0485834, 2.8678003,
+        4.4849099, 5.5568808, 4.5292698, 0.1169475, 4.2397456, 2.7552322,
+        2.7509053, 0.7353640, 5.1187960, 2.0411269, 1.5470969, 2.1533307,
+        2.3605433, 3.4340988, 3.5306485, 2.4870244, 2.5015301, 3.2381477,
+        4.1313862, 5.9747764, 4.5386496, 2.5137752, 5.2268018, 0.8440727,
+        0.3799239, 0.5293398, 0.0000000, 2.0371338, 1.8958053, 0.0733938,
+        3.3923238, 0.5992443, 0.9205800, 3.9655772, 5.3992694, 6.1212150,
+        3.5866836, 6.2633946, 3.4780043, 3.2387210, 2.0777367, 2.7017810,
+        3.0901098, 0.4463392, 5.5778300, 0.4061048, 2.7406309, 5.1938664,
+        2.4789345, 3.8545764, 5.1436714, 5.5683790, 5.8503469, 1.1987353,
+        1.6247202, 5.6414565, 3.7282025, 3.1657206, 3.8503962, 5.1485818,
+        3.3419582, 1.2696753, 2.8518968, 2.6886436, 6.0698884, 3.8959208,
+        4.3692639, 4.5249277, 2.1796068, 3.2483466, 3.4978155, 0.9832885,
+        3.5315023, 4.3655778, 2.6794992, 5.2544420, 4.5954405, 2.2621418,
+        2.8539005, 2.4277593, 4.8729535, 4.6135614, 2.7035154, 4.3589760,
+        5.9389515, 4.9274787, 4.4332387, 0.6869673, 2.4500066, 3.7127639,
+        2.8863700, 0.3162955, 1.4368865, 5.2413645, 0.0982985, 5.4268554,
+        0.4905223, 4.2037186, 3.1429204, 1.3696954, 3.5915675, 0.7677371,
+        4.2170618, 3.7673071, 0.3517086, 0.3540136, 0.9581898, 0.1232828,
+        2.7342886, 5.2290017, 3.8791769, 3.2680695, 5.4278441, 0.6138541,
+        5.7054603, 0.6786889, 3.2483864, 0.8994758, 3.5146290, 0.0287746,
+        4.8172051, 5.3325973, 5.7605579, 6.2013046, 3.1738449, 1.7053924,
+        0.6330341, 3.1909083, 3.6794907, 4.7933610, 0.5212697, 4.1569315,
+        3.2482749, 1.0747264, 5.8971330, 3.7101152, 2.7685894, 5.9182512,
+        4.1212281, 2.8396586, 5.2759745, 3.3465722, 3.4801751, 4.2729777,
+        2.3071222, 1.5035072, 3.6374836, 5.4468120, 2.5558538, 0.7075818,
+        2.7887656, 1.8861142, 2.5219880, 5.2361777, 2.5360737, 2.4515477,
+        2.2647672, 0.8812504, 1.6344462, 0.5454754, 2.6979830, 1.6165554,
+        1.8695956, 2.6694641, 0.7490013, 3.1105972, 4.4384875, 1.5304166,
+        4.9327408, 0.4655185, 2.4748426, 0.0213259, 1.3865538, 0.0081717,
+        1.1886509, 0.8952537, 1.6843712, 1.0988793, 0.8711572, 3.7629093,
+        5.6615138, 5.9022971, 1.3897429, 3.0327137, 2.3625475, 3.2910070,
+        1.6642436, 0.4295011, 2.7415239, 1.0923508, 0.1640358, 5.9984205,
+        2.7055177, 6.0416507, 4.7903915, 0.0461730, 4.2728088, 4.4356194,
+        4.0534637, 3.4702651, 1.3704176, 4.8529200, 1.4327442, 2.3302118,
+        5.5978709, 5.3807748, 2.5285646, 1.9981730, 3.8241692, 5.7189253,
+        5.7120324, 3.7170973, 2.0896078, 5.3599569, 2.7796679, 5.6822331,
+        0.2084724, 3.3453343, 4.5018856, 1.1265867, 2.1144987, 1.1794352,
+        2.0227281, 2.5375066, 3.4467437, 0.3062336, 3.4729184, 1.7266910,
+        1.5174002, 1.5277262, 0.9686124, 6.0093412, 5.8789338, 5.1441345,
+        4.5758041, 1.1046577, 2.2642776, 1.1862024, 0.0075297, 1.9881224,
+        4.3958232, 3.9285942, 3.4121603, 2.7585521, 1.8059588, 3.1520171,
+        4.7849358, 4.7903511, 3.6194660, 4.6977042, 4.0560129, 0.7742111,
+        3.1692252, 2.1819072, 0.5789810, 0.9289656, 1.2451370, 4.2239985,
+        2.7112647, 4.3630684, 1.6134250, 0.0613154, 3.3444332, 1.7554715,
+        5.9453394, 5.6953510, 2.4673100, 0.1561700, 4.2187618, 5.2600982,
+        6.1041123, 0.3577199, 2.8294680, 3.6597688, 4.3142726, 4.5203293,
+        4.0843265, 4.5673388, 2.3489542, 3.6541880, 0.7295941, 0.3622530,
+        6.1560465, 1.7896003, 3.7383338, 6.0454361, 1.1672793, 1.2129049,
+        2.1466132, 5.8615704, 2.4546365, 1.7166712, 0.9547117, 2.4951084,
+        2.3544507, 0.8238180, 2.7334414, 0.5749942, 3.8618151, 0.0689837,
+        3.6019012, 4.9620190, 1.4788531, 2.8149909, 3.5773830, 0.3857966,
+        3.1182750, 4.0357856, 1.3902536, 5.2593808, 6.1014456, 5.3179177,
+        3.1792883, 1.7522271, 4.6911344, 1.4886775, 6.0151778, 3.8972087,
+        3.7715583, 1.0845061, 0.5676653, 1.6038597, 5.3945577, 5.7244031,
+        4.3959286, 4.5564551, 1.4444168, 3.6194506, 5.0933266, 2.5374227,
+        6.2105471, 0.5654792, 2.0165320, 3.2132771, 0.3808010, 4.5596317,
+        3.4969429, 3.3260664, 5.2149334, 5.3957421, 4.9576149, 1.9970040,
+        2.8413032, 4.7263877, 0.6902815, 0.6895316, 1.6957291, 3.2963937,
+        6.1113470, 4.4636294, 1.9594738, 1.8312791, 5.3429527, 5.7280497,
+        4.0166905, 1.6045389, 0.5571039, 5.2669152, 3.6738954, 5.9571429,
+        0.3834561, 3.6734096, 1.7913869, 5.2007946, 1.2000032, 2.7804978,
+        2.4718774, 5.1935175, 4.2529065, 1.3044083, 1.9987109, 0.8407592,
+        4.2189258, 3.5876427, 1.0666779, 0.9277486, 2.9912971, 5.7057758,
+        3.4694180, 0.2069675, 0.3384307, 5.0583614, 2.8360719, 2.4042372,
+        4.9614777, 2.2888819, 3.3448533, 4.4714710, 5.4756485, 2.0652177,
+        4.0848120, 6.1250762, 0.4773170, 3.6883502, 2.6005256, 1.9423615,
+        1.6577182, 4.7674690, 6.2531264, 1.1722630, 4.9080805, 1.2302350,
+        6.2351753, 5.0407581, 2.6654950, 4.5795867, 3.1312479, 5.0830358,
+        2.2400117, 0.4602021, 3.7133088, 5.7188788, 1.2174673, 2.7166470,
+        4.7071094, 0.2462034, 5.9459353, 4.7983010, 3.5111731, 1.1551193,
+        3.1287047, 3.2537199, 6.2470131, 5.3711915, 6.0469623, 4.2659122,
+        2.5352740, 5.8746469, 3.0126903, 1.4563896, 2.4899651, 4.4301324,
+        3.5095299, 4.7540509, 6.2547920, 6.0471349, 3.3619258, 6.0561746,
+        0.7264988, 0.3232592, 1.9122808, 3.6454528, 3.3361480, 5.6624574,
+        3.3963785, 2.7142142, 3.4096772, 4.4762342, 0.1047703, 5.0323343,
+        0.8954125, 3.0063438, 1.6137441, 2.3190715, 4.1579916, 1.0656836,
+        1.7516517, 1.2454643, 1.2256706, 2.0535941, 5.5313259, 2.9600203,
+        2.5382144, 1.1261446, 6.0879353, 2.5601199, 5.3060708, 3.8662016,
+        2.3663172, 5.5114955, 4.9313732, 2.9213939, 5.1143679, 5.6450910,
+        2.6969853, 2.1006537, 3.7488443, 5.6673754, 4.4112136, 2.3716204,
+        4.6178643, 5.9948046, 3.4105954, 3.3935850, 1.9547595, 0.4475800,
+        1.1434170, 0.5842667, 2.9121888, 0.0586379, 5.7492774, 4.0384655,
+        0.0089162, 0.1909163, 1.3098570, 2.8586366, 0.7996361, 0.0543350,
+        4.5683759, 2.2249794, 4.9036865, 2.7435946, 2.7429546, 0.3092155,
+        0.3118464, 0.5723993, 3.7324447, 1.5147758, 5.2864780, 5.3860266,
+        6.0545540, 3.0718480, 1.3842492, 1.4213108, 3.3727372, 4.7884765,
+        2.1838288, 2.8980046, 4.0169897, 5.7637923, 1.0151904, 4.4964699,
+        3.6300404, 2.7224978, 5.5558613, 2.4696170, 1.1245340, 3.9793522,
+        3.9207111, 2.0605178, 5.0451799, 6.2799046, 6.1636676, 0.7981966,
+        1.4592079, 0.1484872, 3.8166117, 0.6962355, 2.5601436, 5.5548184,
+        3.4440198, 2.3185147, 1.3090764, 2.7705283, 6.0079576, 0.7792778,
+        2.9578927, 5.3840384, 0.2726304, 4.3456090, 6.1511471, 1.7798247,
+        0.8405677, 4.3057392, 5.7142715, 3.8382030, 5.6547587, 1.2153801,
+        4.7401894, 2.1756202, 2.6303011, 0.9784166, 5.1459324, 3.9265103,
+        4.6405120, 5.0586705, 0.4223724, 5.9739917, 3.1263686, 4.7447217,
+        4.6646686, 5.2221411, 0.9833301, 2.8733554, 3.8836400, 5.8570808,
+       -5.2470141, 5.6261119, 3.6600718, 3.6615062, 5.3716581, 0.2190677,
+       -5.5632585, 2.5618482, 0.2285950, 4.6881858, 0.9728179, 0.9042027,
+       -3.8073530, 1.5989503, 2.0367209, 2.5245268, 2.5533189, 2.4265105,
+       -3.8314979, 1.0486053, 1.1818174, 0.5945707, 2.0306392, 4.8355201,
+       -1.4710068, 4.6518534, 4.3531065, 5.1778361, 5.2023364, 1.8432851,
+       -1.9438243, 3.2862931, 2.0439139, 5.2266206, 5.0912323, 3.4997233,
+       -1.6522518, 4.2761236, 1.4680860, 2.8678051, 2.4163051, 3.3841326,
+       -6.2310582, 4.7451897, 6.1603795, 1.4751828, 3.3210347, 0.3231823,
+       -4.7555888, 3.7823504, 5.3857498, 6.2095284, 5.8401232, 2.5730582,
+       -0.0021455, 3.3984387, 1.3052100, 1.3777994, 2.0471011, 0.6028680,
+       -4.6968925, 4.7030205, 3.4136510, 2.1245480, 5.2297066, 3.4719134,
+       -6.0164208, 5.6098372, 2.2399783, 3.4331443, 2.1782657, 3.9131853,
+       -5.0053405, 4.6864702, 0.7887674, 5.1672539, 0.1580253, 2.6039335,
+       -4.5955687, 4.9095176, 2.3077255, 4.6801428, 5.6062801, 1.5243220,
+       -0.8142818, 1.4141432, 2.1992023, 1.8038058, 5.8275790, 0.3224138,
+       -3.7238350, 1.0235240, 5.2678588, 1.0528164, 3.1554195, 6.2789723,
+       -2.2330890, 0.2957980, 1.3424690, 2.4996969, 2.0964990, 1.4426353,
+       -5.8818165, 4.2926017, 6.0451393, 2.7518666, 5.9083095, 0.0366581,
+       -3.8346722, 5.0333074, 1.4638661, 5.8588735, 4.7957215, 5.1927356,
+       -3.6031780, 4.9799375, 2.0674268, 1.4040530, 1.9627813, 3.6726693,
+       -5.2145043, 1.8250297, 2.5293238, 5.4164658, 3.8625225, 6.2278165,
+       -1.2798778, 5.1975080, 4.2465638, 1.5641957, 2.9894493, 2.5074636,
+       -3.7663816, 5.0298329, 0.6601666, 5.1612735, 5.2847013, 2.2274284,
+       -2.7022061, 3.5954850, 4.4034117, 4.6650751, 4.7619266, 2.4449681,
+       -2.6973871, 6.0088907, 3.6000853, 5.3389611
+};

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c

+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+#define BIQUAD_DEFINE_TEST(suffix, instance_name, config_suffix, output_type)    \
+   JTEST_DEFINE_TEST(arm_biquad_cascade_##config_suffix##_##suffix##_test,       \
+         arm_biquad_cascade_##config_suffix##_##suffix)                          \
+   {                                                                             \
+      instance_name biquad_inst_fut = { 0 };                                     \
+      instance_name biquad_inst_ref = { 0 };                                     \
+                                                                                 \
+      TEMPLATE_DO_ARR_DESC(                                                      \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes             \
+            ,                                                                    \
+         TEMPLATE_DO_ARR_DESC(                                                   \
+               numstages_idx, uint16_t, numStages, filtering_numstages           \
+               ,                                                                 \
+               /* Initialize the BIQUAD Instances */                             \
+               arm_biquad_cascade_##config_suffix##_init_##suffix(               \
+                     &biquad_inst_fut, numStages,                                \
+                     (output_type*)filtering_coeffs_b_##suffix,                  \
+                     (void *) filtering_pState);                                 \
+                                                                                 \
+               /* Display test parameter values */                               \
+               JTEST_DUMP_STRF("Block Size: %d\n"                                \
+                               "Number of Stages: %d\n",                         \
+                               (int)blockSize,                                   \
+                               (int)numStages);                                  \
+                                                                                 \
+               JTEST_COUNT_CYCLES(                                               \
+                     arm_biquad_cascade_##config_suffix##_##suffix(              \
+                           &biquad_inst_fut,                                     \
+                           (void *) filtering_##suffix##_inputs,                 \
+                           (void *) filtering_output_fut,                        \
+                           blockSize));                                          \
+                                                                                 \
+               arm_biquad_cascade_##config_suffix##_init_##suffix(               \
+                     &biquad_inst_ref, numStages,                                \
+                     (output_type*)filtering_coeffs_b_##suffix,                  \
+                     (void *) filtering_pState);                                 \
+                                                                                 \
+               ref_biquad_cascade_##config_suffix##_##suffix(                    \
+                     &biquad_inst_ref,                                           \
+                     (void *) filtering_##suffix##_inputs,                       \
+                     (void *) filtering_output_ref,                              \
+                     blockSize);                                                 \
+                                                                                 \
+               FILTERING_SNR_COMPARE_INTERFACE(                                  \
+                     blockSize,                                                  \
+                     output_type)));                                             \
+                                                                                 \
+            return JTEST_TEST_PASSED;                                            \
+   }
+
+#define BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(suffix, config_suffix, speed, output_type)   \
+   JTEST_DEFINE_TEST(arm_biquad_cascade_##config_suffix##speed##_##suffix##_test,      \
+         arm_biquad_cascade_##config_suffix##speed##_##suffix)                         \
+   {                                                                                   \
+      arm_biquad_casd_##config_suffix##_inst_##suffix biquad_inst_fut = { 0 };         \
+      arm_biquad_casd_##config_suffix##_inst_##suffix biquad_inst_ref = { 0 };         \
+                                                                                       \
+      TEMPLATE_DO_ARR_DESC(                                                            \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes                   \
+            ,                                                                          \
+         TEMPLATE_DO_ARR_DESC(                                                         \
+               numstages_idx, uint16_t, numStages, filtering_numstages                 \
+               ,                                                                       \
+            TEMPLATE_DO_ARR_DESC(                                                      \
+                  postshifts_idx, uint8_t, postShift, filtering_postshifts             \
+                  ,                                                                    \
+                  /* Display test parameter values */                                  \
+                  JTEST_DUMP_STRF("Block Size: %d\n"                                   \
+                                  "Number of Stages: %d\n"                             \
+                                  "Post Shift: %d\n",                                  \
+                                  (int)blockSize,                                      \
+                                  (int)numStages,                                      \
+                                  (int)postShift);                                     \
+                                                                                       \
+                  /* Initialize the BIQUAD Instances */                                \
+                  arm_biquad_cascade_##config_suffix##_init_##suffix(                  \
+                        &biquad_inst_fut, numStages,                                   \
+                        (output_type*)filtering_coeffs_b_##suffix,                     \
+                        (void *) filtering_pState, postShift);                         \
+                                                                                       \
+                  JTEST_COUNT_CYCLES(                                                  \
+                        arm_biquad_cascade_##config_suffix##speed##_##suffix(          \
+                              &biquad_inst_fut,                                        \
+                              (void *) filtering_##suffix##_inputs,                    \
+                              (void *) filtering_output_fut,                           \
+                              blockSize));                                             \
+                                                                                       \
+                  arm_biquad_cascade_##config_suffix##_init_##suffix(                  \
+                        &biquad_inst_ref, numStages,                                   \
+                        (output_type*)filtering_coeffs_b_##suffix,                     \
+                        (void *) filtering_pState, postShift);                         \
+                                                                                       \
+                  ref_biquad_cascade_##config_suffix##speed##_##suffix(                \
+                        &biquad_inst_ref,                                              \
+                        (void *) filtering_##suffix##_inputs,                          \
+                        (void *) filtering_output_ref,                                 \
+                        blockSize);                                                    \
+                                                                                       \
+                  FILTERING_SNR_COMPARE_INTERFACE(                                     \
+                        blockSize,                                                     \
+                        output_type))));                                               \
+                                                                                       \
+            return JTEST_TEST_PASSED;                                                  \
+   }
+
+
+JTEST_DEFINE_TEST(arm_biquad_cas_df1_32x64_q31_test,
+      arm_biquad_cas_df1_32x64_q31)
+{
+   arm_biquad_cas_df1_32x64_ins_q31 biquad_inst_fut = { 0 };
+   arm_biquad_cas_df1_32x64_ins_q31 biquad_inst_ref = { 0 };
+
+   TEMPLATE_DO_ARR_DESC(
+         blocksize_idx, uint32_t, blockSize, filtering_blocksizes
+         ,
+      TEMPLATE_DO_ARR_DESC(
+            numstages_idx, uint16_t, numStages, filtering_numstages
+            ,
+         TEMPLATE_DO_ARR_DESC(
+               postshifts_idx, uint8_t, postShift, filtering_postshifts
+               ,
+               /* Initialize the BIQUAD Instances */
+               arm_biquad_cas_df1_32x64_init_q31(
+                     &biquad_inst_fut, numStages,
+                     (q31_t*)filtering_coeffs_b_q31,
+                     (void *) filtering_pState, postShift);
+
+              /* Display test parameter values */
+              JTEST_DUMP_STRF("Block Size: %d\n"
+                              "Number of Stages: %d\n",
+                              (int)blockSize,
+                              (int)numStages);
+
+               JTEST_COUNT_CYCLES(
+                     arm_biquad_cas_df1_32x64_q31(
+                           &biquad_inst_fut,
+                           (void *) filtering_q31_inputs,
+                           (void *) filtering_output_fut,
+                           blockSize));
+
+               arm_biquad_cas_df1_32x64_init_q31(
+                     &biquad_inst_ref, numStages,
+                     (q31_t*)filtering_coeffs_b_q31,
+                     (void *) filtering_pState, postShift);
+
+               ref_biquad_cas_df1_32x64_q31(
+                     &biquad_inst_ref,
+                     (void *) filtering_q31_inputs,
+                     (void *) filtering_output_ref,
+                     blockSize);
+
+               FILTERING_SNR_COMPARE_INTERFACE(
+                     blockSize,
+                     q31_t))));
+
+         return JTEST_TEST_PASSED;
+}
+
+JTEST_DEFINE_TEST(arm_biquad_cascade_df2T_f64_test,
+     arm_biquad_cascade_df2T_f64)
+{
+  arm_biquad_cascade_df2T_instance_f64 biquad_inst_fut = { 0 };
+  arm_biquad_cascade_df2T_instance_f64 biquad_inst_ref = { 0 };
+
+  TEMPLATE_DO_ARR_DESC(
+        blocksize_idx, uint32_t, blockSize, filtering_blocksizes
+        ,
+     TEMPLATE_DO_ARR_DESC(
+           numstages_idx, uint16_t, numStages, filtering_numstages
+           ,
+           /* Display test parameter values */
+           JTEST_DUMP_STRF("Block Size: %d\n"
+                           "Number of Stages: %d\n",
+                           (int)blockSize,
+                           (int)numStages);
+
+           /* Initialize the BIQUAD Instances */
+           arm_biquad_cascade_df2T_init_f64(
+                 &biquad_inst_fut, numStages,
+                 (float64_t*)filtering_coeffs_b_f64,
+                 (void *) filtering_pState);
+
+           JTEST_COUNT_CYCLES(
+                 arm_biquad_cascade_df2T_f64(
+                       &biquad_inst_fut,
+                       (void *) filtering_f64_inputs,
+                       (void *) filtering_output_fut,
+                       blockSize));
+
+           arm_biquad_cascade_df2T_init_f64(
+                 &biquad_inst_ref, numStages,
+                 (float64_t*)filtering_coeffs_b_f64,
+                 (void *) filtering_pState);
+
+           ref_biquad_cascade_df2T_f64(
+                 &biquad_inst_ref,
+                 (void *) filtering_f64_inputs,
+                 (void *) filtering_output_ref,
+                 blockSize);
+
+           FILTERING_DBL_SNR_COMPARE_INTERFACE(
+                 blockSize,
+                 float64_t)));
+
+        return JTEST_TEST_PASSED;
+}
+
+
+BIQUAD_DEFINE_TEST(f32,arm_biquad_casd_df1_inst_f32, df1,float32_t);
+BIQUAD_DEFINE_TEST(f32,arm_biquad_cascade_df2T_instance_f32,df2T,float32_t);
+BIQUAD_DEFINE_TEST(f32,arm_biquad_cascade_stereo_df2T_instance_f32,stereo_df2T,float32_t);
+BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q31,df1,,q31_t);
+BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q15,df1,,q15_t);
+BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q31,df1,_fast,q31_t);
+BIQUAD_WITH_POSTSHIFT_DEFINE_TEST(q15,df1,_fast,q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(biquad_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+   JTEST_TEST_CALL(arm_biquad_cascade_df1_f32_test);
+   JTEST_TEST_CALL(arm_biquad_cascade_df2T_f32_test);
+   JTEST_TEST_CALL(arm_biquad_cascade_stereo_df2T_f32_test);
+   JTEST_TEST_CALL(arm_biquad_cascade_df2T_f64_test);
+   JTEST_TEST_CALL(arm_biquad_cascade_df1_q31_test);
+   JTEST_TEST_CALL(arm_biquad_cascade_df1_q15_test);
+   JTEST_TEST_CALL(arm_biquad_cascade_df1_fast_q31_test);
+   JTEST_TEST_CALL(arm_biquad_cascade_df1_fast_q15_test);
+   JTEST_TEST_CALL(arm_biquad_cas_df1_32x64_q31_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c

+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Header Stuff */
+/*--------------------------------------------------------------------------------*/
+
+#define CONV_MAX_INPUT_ELTS  32
+#define CONV_MAX_OUTPUT_ELTS (CONV_MAX_INPUT_ELTS * 2)
+
+#define CONV_TEST_VALID_PARTIAL_PARAMS(input_a_len, input_b_len,           \
+                                       first_index, num_points)            \
+    (((((input_a_len) + (input_b_len) - 1)) >= num_points + first_index )  \
+    && (num_points > 0))
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define CONV_arm_conv_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \
+    PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut)
+
+#define CONV_ref_conv_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \
+    PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref)
+
+#define CONV_arm_conv_opt_INPUT_INTERFACE(              \
+    input_a, input_a_len,                               \
+    input_b, input_b_len)                               \
+    PAREN(input_a, input_a_len, input_b, input_b_len,   \
+          (void*) filtering_output_fut,                 \
+          (void*) filtering_scratch,                    \
+          (void*) filtering_scratch2)
+
+#define CONV_ref_conv_opt_INPUT_INTERFACE(              \
+    input_a, input_a_len,                               \
+    input_b, input_b_len)                               \
+    PAREN(input_a, input_a_len, input_b, input_b_len,   \
+          (void*) filtering_output_ref,                 \
+          (void*) filtering_scratch,                    \
+          (void*) filtering_scratch2)
+
+#define CONV_arm_conv_fast_INPUT_INTERFACE(input_a, input_a_len,        \
+                                           input_b, input_b_len)        \
+    PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut)
+
+#define CONV_ref_conv_fast_INPUT_INTERFACE(input_a, input_a_len,        \
+                                           input_b, input_b_len)        \
+    PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref)
+
+#define CONV_arm_conv_fast_opt_INPUT_INTERFACE(         \
+    input_a, input_a_len,                               \
+    input_b, input_b_len)                               \
+    PAREN(input_a, input_a_len, input_b, input_b_len,   \
+          (void*) filtering_output_fut,                 \
+          (void*) filtering_scratch,                    \
+          (void*) filtering_scratch2)
+
+#define CONV_ref_conv_fast_opt_INPUT_INTERFACE(         \
+    input_a, input_a_len,                               \
+    input_b, input_b_len)                               \
+    PAREN(input_a, input_a_len, input_b, input_b_len,   \
+          (void*) filtering_output_ref,                 \
+          (void*) filtering_scratch,                    \
+          (void*) filtering_scratch2)
+
+#define CONV_arm_conv_partial_INPUT_INTERFACE(input_a, input_a_len,     \
+                                              input_b, input_b_len,     \
+                                              first_index, num_points)  \
+    PAREN(input_a, input_a_len, input_b, input_b_len,                   \
+          (void*)filtering_output_fut, first_index, num_points)
+
+#define CONV_ref_conv_partial_INPUT_INTERFACE(input_a, input_a_len,     \
+                                              input_b, input_b_len,     \
+                                              first_index, num_points)  \
+    PAREN(input_a, input_a_len, input_b, input_b_len,                   \
+          (void*)filtering_output_ref, first_index, num_points)
+
+#define CONV_arm_conv_partial_fast_INPUT_INTERFACE(input_a, input_a_len,   \
+                                              input_b, input_b_len,        \
+                                              first_index, num_points)     \
+    PAREN(input_a, input_a_len, input_b, input_b_len,                      \
+          (void*)filtering_output_fut, first_index, num_points)
+
+#define CONV_ref_conv_partial_fast_INPUT_INTERFACE(input_a, input_a_len,   \
+                                              input_b, input_b_len,        \
+                                              first_index, num_points)     \
+    PAREN(input_a, input_a_len, input_b, input_b_len,                      \
+          (void*)filtering_output_ref, first_index, num_points)
+
+#define CONV_arm_conv_partial_opt_INPUT_INTERFACE(input_a, input_a_len, \
+                                              input_b, input_b_len,     \
+                                              first_index, num_points)  \
+    PAREN(input_a, input_a_len, input_b, input_b_len,                   \
+          (void*)filtering_output_fut, first_index, num_points,         \
+          (void*) filtering_scratch,                                    \
+          (void*) filtering_scratch2)
+
+#define CONV_ref_conv_partial_opt_INPUT_INTERFACE(input_a, input_a_len, \
+                                              input_b, input_b_len,     \
+                                              first_index, num_points)  \
+    PAREN(input_a, input_a_len, input_b, input_b_len,                   \
+          (void*)filtering_output_ref, first_index, num_points,         \
+          (void*) filtering_scratch,                                    \
+          (void*) filtering_scratch2)
+
+#define CONV_arm_conv_partial_fast_opt_INPUT_INTERFACE(input_a, input_a_len,  \
+                                              input_b, input_b_len,           \
+                                              first_index, num_points)        \
+    PAREN(input_a, input_a_len, input_b, input_b_len,                         \
+          (void*)filtering_output_fut, first_index, num_points,               \
+          (void*) filtering_scratch,                                          \
+          (void*) filtering_scratch2)
+
+#define CONV_ref_conv_partial_fast_opt_INPUT_INTERFACE(input_a, input_a_len,  \
+                                              input_b, input_b_len,           \
+                                              first_index, num_points)        \
+    PAREN(input_a, input_a_len, input_b, input_b_len,                         \
+          (void*)filtering_output_ref, first_index, num_points,               \
+          (void*) filtering_scratch,                                          \
+          (void*) filtering_scratch2)
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Inputs */
+/*--------------------------------------------------------------------------------*/
+
+/* The following symbols alias the filtering_q31_inputs array:
+ *
+ * - filtering_q15_inputs
+ * - filtering_q7_inputs
+ *
+ * The aliasing conflicts with the instantiation of #ARR_DESC_t structs.
+ *
+ * These macro-level aliases allow the #CONV_DEFINE_RAND_INPUT_ARR_DESCS() macro
+ * to correctly select the filtering_q31_input or filtering_f32_input array,
+ * within a template, by type_suffix.
+ *
+ */
+#define CONV_f32_INPUTS filtering_f32_inputs
+#define CONV_q31_INPUTS filtering_q31_inputs
+#define CONV_q15_INPUTS filtering_q31_inputs
+#define CONV_q7_INPUTS  filtering_q31_inputs
+
+/**
+ *  Defines #ARR_DESC_t objects that wrap existing, type-specific, common
+ *  inputs.
+ */
+#define CONV_DEFINE_RAND_INPUT_ARR_DESCS(type_suffix)           \
+    ARR_DESC_DEFINE_USING_ARR(                                  \
+        TYPE_FROM_ABBREV(type_suffix),                          \
+        conv_input_rand1_##type_suffix,                         \
+        CONV_##type_suffix##_INPUTS,                            \
+        0,                                                      \
+        CONV_MAX_INPUT_ELTS);                                   \
+                                                                \
+    ARR_DESC_DEFINE_USING_ARR(                                  \
+        TYPE_FROM_ABBREV(type_suffix),                          \
+        conv_input_rand2_##type_suffix,                         \
+        CONV_##type_suffix##_INPUTS,                            \
+        1,                                                      \
+        CONV_MAX_INPUT_ELTS)  /* Note the lacking semicolon */
+
+CONV_DEFINE_RAND_INPUT_ARR_DESCS(f32);
+CONV_DEFINE_RAND_INPUT_ARR_DESCS(q31);
+CONV_DEFINE_RAND_INPUT_ARR_DESCS(q15);
+CONV_DEFINE_RAND_INPUT_ARR_DESCS(q7);
+ARR_DESC_DEFINE(float32_t, conv_input_zeros, CONV_MAX_INPUT_ELTS, CURLY(0));
+
+/**
+ *  Define Input #ARR_DESC_t arrays by type suffix.
+ *
+ *  Taking inputs in parallel from the 'a' and 'b' arrays yields the following
+ *  test cases (star is convolution):
+ *
+ *  - zero_array   * zero_array
+ *  - zero_array   * random_array
+ *  - random_array * zero_array
+ *  - random_array * different_random_arary
+ */
+#define CONV_DEFINE_ALL_INPUTS(type_suffix)                 \
+    ARR_DESC_DEFINE(ARR_DESC_t *,                           \
+                    conv_##type_suffix##_a_inputs,          \
+                    4,                                      \
+                    CURLY(                                  \
+                        &conv_input_zeros,                  \
+                        &conv_input_zeros,                  \
+                        &conv_input_rand1_##type_suffix,    \
+                        &conv_input_rand1_##type_suffix     \
+                        ));                                 \
+    ARR_DESC_DEFINE(ARR_DESC_t *,                           \
+                    conv_##type_suffix##_b_inputs,          \
+                    4,                                      \
+                    CURLY(                                  \
+                        &conv_input_zeros,                  \
+                        &conv_input_rand1_##type_suffix,    \
+                        &conv_input_zeros,                  \
+                        &conv_input_rand2_##type_suffix     \
+                        )) /* Note the lacking semicolon */
+
+CONV_DEFINE_ALL_INPUTS(f32);
+CONV_DEFINE_ALL_INPUTS(q31);
+CONV_DEFINE_ALL_INPUTS(q15);
+CONV_DEFINE_ALL_INPUTS(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Lengths */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ *  The conv_lens_a and conv_lens_b #ARR_DESC_t objects are accessed in parallel
+ *  to provide convolution-length pairs. Taken in parallel they provide the
+ *  following cases:
+ *
+ *  - 1 * 1    : Shortest convolution possible.
+ *  - 1 * 2    : Short convolution   , one side is degenerate .
+ *  - 17 * 1   : Medium convolution  , one side is degenerate .
+ *  - 15 * MAX : Longest convolution , one side is degenerate .
+ *  MAX * MAX  : Longest convolution.
+ */
+ARR_DESC_DEFINE(uint32_t,
+                conv_lens_a,
+                5,
+                CURLY(
+                    1,
+                    1,
+                    17,
+                    15,
+                    CONV_MAX_INPUT_ELTS
+                    ));
+
+ARR_DESC_DEFINE(uint32_t,
+                conv_lens_b,
+                5,
+                CURLY(
+                    1,
+                    2,
+                    1,
+                    CONV_MAX_INPUT_ELTS,
+                    CONV_MAX_INPUT_ELTS
+                    ));
+
+/*--------------------------------------------------------------------------------*/
+/* Partial Indexing */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(uint32_t,
+                first_index_arr_desc,
+                4,
+                CURLY(
+                    0,
+                    1,
+                    CONV_MAX_INPUT_ELTS / 2,
+                    CONV_MAX_INPUT_ELTS
+                    ));
+
+ARR_DESC_DEFINE(uint32_t,
+                num_points_arr_desc,
+                3,
+                CURLY(
+                    1,
+                    CONV_MAX_OUTPUT_ELTS / 2,
+                    CONV_MAX_OUTPUT_ELTS
+                    ));
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Tests */
+/*--------------------------------------------------------------------------------*/
+
+#define CONV_TEST_TEMPLATE(fut, fut_arg_interface,                            \
+                           ref, ref_arg_interface,                            \
+                           suffix, output_type)                               \
+    JTEST_DEFINE_TEST(fut##_tests, fut)                                       \
+    {                                                                         \
+        TEMPLATE_DO_ARR_DESC(                                                 \
+            input_idx, ARR_DESC_t *, input_ptr, conv_##suffix##_a_inputs      \
+            ,                                                                 \
+            void * input_a_ptr = input_ptr->data_ptr;                         \
+            void * input_b_ptr = ARR_DESC_ELT(                                \
+                ARR_DESC_t *, input_idx,                                      \
+                &(conv_##suffix##_b_inputs))->data_ptr;                       \
+                                                                              \
+            TEMPLATE_DO_ARR_DESC(                                             \
+                conv_len_idx, uint32_t, conv_len_a, conv_lens_a               \
+                ,                                                             \
+                uint32_t conv_len_b = ARR_DESC_ELT(                           \
+                    uint32_t, conv_len_idx, &(conv_lens_b));                  \
+                                                                              \
+                JTEST_DUMP_STRF("Input A Length: %d\n"                        \
+                                "Input B Length: %d\n",                       \
+                                (int)conv_len_a,                              \
+                                (int)conv_len_b);                             \
+                                                                              \
+                TEST_CALL_FUT_AND_REF(                                        \
+                    fut, fut_arg_interface(                                   \
+                        input_a_ptr, conv_len_a, input_b_ptr, conv_len_b),    \
+                    ref, ref_arg_interface(                                   \
+                        input_a_ptr, conv_len_a, input_b_ptr, conv_len_b));   \
+                                                                              \
+                FILTERING_SNR_COMPARE_INTERFACE(                              \
+                    conv_len_a + conv_len_b - 1,                              \
+                    output_type)));                                           \
+                                                                              \
+        return JTEST_TEST_PASSED;                                             \
+    }                                                                         \
+                                                                              \
+
+#define CONV_PARTIAL_TEST_TEMPLATE(fut, fut_arg_interface,                    \
+                                   ref, ref_arg_interface,                    \
+                                   suffix, output_type)                       \
+    JTEST_DEFINE_TEST(fut##_tests, fut)                                       \
+    {                                                                         \
+        TEMPLATE_DO_ARR_DESC(                                                 \
+            input_idx, ARR_DESC_t *, input_ptr, conv_##suffix##_a_inputs      \
+            ,                                                                 \
+            void * input_a_ptr = input_ptr->data_ptr;                         \
+            void * input_b_ptr = ARR_DESC_ELT(                                \
+                ARR_DESC_t *, input_idx,                                      \
+                &(conv_##suffix##_b_inputs))->data_ptr;                       \
+            TEMPLATE_DO_ARR_DESC(                                             \
+                conv_len_idx, uint32_t, conv_len_a, conv_lens_a               \
+                ,                                                             \
+                uint32_t conv_len_b = ARR_DESC_ELT(                           \
+                    uint32_t, conv_len_idx, &(conv_lens_b));                  \
+                                                                              \
+                TEMPLATE_DO_ARR_DESC(                                         \
+                    first_index_idx, uint32_t, first_index,                   \
+                    first_index_arr_desc                                      \
+                    ,                                                         \
+                    TEMPLATE_DO_ARR_DESC(                                     \
+                        num_points_idx, uint32_t, num_points,                 \
+                        num_points_arr_desc                                   \
+                        ,                                                     \
+                        if (CONV_TEST_VALID_PARTIAL_PARAMS(                   \
+                                conv_len_a, conv_len_b,                       \
+                                first_index, num_points))                     \
+                        {                                                     \
+                            /* Display test parameter values */               \
+                            JTEST_DUMP_STRF("Input A Length: %d\n"            \
+                                            "Input B Length: %d\n"            \
+                                            "First Sample Index: %d\n"        \
+                                            "Number of Output Points: %d\n",  \
+                                            (int)conv_len_a,                  \
+                                            (int)conv_len_b,                  \
+                                            (int)first_index,                 \
+                                            (int)num_points);                 \
+                                                                              \
+                           memset(filtering_output_ref,0,                     \
+                                 (2*CONV_MAX_INPUT_ELTS)*sizeof(output_type)); \
+                           memset(filtering_output_fut,0,                     \
+                                 (2*CONV_MAX_INPUT_ELTS)*sizeof(output_type)); \
+                                                                              \
+                            TEST_CALL_FUT_AND_REF(                            \
+                                fut, fut_arg_interface(                       \
+                                    input_a_ptr, conv_len_a,                  \
+                                    input_b_ptr, conv_len_b,                  \
+                                    first_index, num_points),                 \
+                                ref, ref_arg_interface(                       \
+                                    input_a_ptr, conv_len_a,                  \
+                                    input_b_ptr, conv_len_b,                  \
+                                    first_index, num_points));                \
+                                                                              \
+                            FILTERING_SNR_COMPARE_INTERFACE_OFFSET(           \
+                                first_index,                                  \
+                                num_points,                                   \
+                                output_type);                                 \
+                        } else {                                              \
+                            /* FUT should return ARM_MATH_ARGUMENT_ERROR*/    \
+                            /* if first_index and num_points don't make */    \
+                            /* sense*/                                        \
+                                                                              \
+                            arm_status conv_test_retval;                      \
+                            TEST_CALL_FUT(                                    \
+                                conv_test_retval = fut,                       \
+                                fut_arg_interface(                            \
+                                    input_a_ptr, conv_len_a,                  \
+                                    input_b_ptr, conv_len_b,                  \
+                                    first_index, num_points));                \
+                                                                              \
+                            if (conv_test_retval != ARM_MATH_ARGUMENT_ERROR) { \
+                                JTEST_DUMP_STR("FUT failed to raise error."); \
+                                /* return JTEST_TEST_FAILED; */               \
+                            }                                                 \
+                        }))));                                                \
+                                                                              \
+        return JTEST_TEST_PASSED;                                             \
+    }
+
+#define CONV_DEFINE_TEST(fn_name, suffix, output_type, test_template)   \
+    test_template(                                                      \
+        arm_##fn_name##_##suffix,                                       \
+        CONV_arm_##fn_name##_INPUT_INTERFACE,                           \
+        ref_##fn_name##_##suffix,                                       \
+        CONV_ref_##fn_name##_INPUT_INTERFACE,                           \
+        suffix,                                                         \
+        output_type                                                     \
+        ) /* Note the lacking semicolon*/
+
+/* Tests on functions without partial outputs */
+CONV_DEFINE_TEST(conv          , f32, float32_t, CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv          , q31, q31_t    , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv          , q15, q15_t    , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv          , q7 , q7_t     , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_opt      , q15, q15_t    , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_opt      , q7 , q7_t     , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_fast     , q31, q31_t    , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_fast     , q15, q15_t    , CONV_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_fast_opt , q15, q15_t    , CONV_TEST_TEMPLATE);
+
+/* Tests on functions with partial outputs  */
+CONV_DEFINE_TEST(conv_partial          , f32, float32_t, CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial          , q31, q31_t    , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial          , q15, q15_t    , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial          , q7 , q7_t     , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_fast     , q31, q31_t    , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_fast     , q15, q15_t    , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_fast_opt , q15, q15_t    , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_opt      , q15, q15_t    , CONV_PARTIAL_TEST_TEMPLATE);
+CONV_DEFINE_TEST(conv_partial_opt      , q7 , q7_t     , CONV_PARTIAL_TEST_TEMPLATE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(conv_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_conv_f32_tests);
+    JTEST_TEST_CALL(arm_conv_q31_tests);
+    JTEST_TEST_CALL(arm_conv_q15_tests);
+    JTEST_TEST_CALL(arm_conv_q7_tests);
+
+    JTEST_TEST_CALL(arm_conv_opt_q15_tests);
+    JTEST_TEST_CALL(arm_conv_opt_q7_tests);
+
+    JTEST_TEST_CALL(arm_conv_fast_q31_tests);
+    JTEST_TEST_CALL(arm_conv_fast_q15_tests);
+
+    JTEST_TEST_CALL(arm_conv_fast_opt_q15_tests);
+
+    JTEST_TEST_CALL(arm_conv_partial_f32_tests);
+    JTEST_TEST_CALL(arm_conv_partial_q31_tests);
+    JTEST_TEST_CALL(arm_conv_partial_q15_tests);
+    JTEST_TEST_CALL(arm_conv_partial_q7_tests);
+
+    JTEST_TEST_CALL(arm_conv_partial_fast_q31_tests);
+    JTEST_TEST_CALL(arm_conv_partial_fast_q15_tests);
+
+    JTEST_TEST_CALL(arm_conv_partial_fast_opt_q15_tests);
+
+    JTEST_TEST_CALL(arm_conv_partial_opt_q15_tests);
+    JTEST_TEST_CALL(arm_conv_partial_opt_q7_tests);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c

+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Header Stuff */
+/*--------------------------------------------------------------------------------*/
+
+#define CORRELATE_MAX_INPUT_ELTS  32
+#define CORRELATE_MAX_OUTPUT_ELTS (CORRELATE_MAX_INPUT_ELTS * 2)
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define CORRELATE_arm_correlate_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \
+    PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut)
+
+#define CORRELATE_ref_correlate_INPUT_INTERFACE(input_a, input_a_len, input_b, input_b_len) \
+    PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref)
+
+#define CORRELATE_arm_correlate_opt_INPUT_INTERFACE(    \
+    input_a, input_a_len,                               \
+    input_b, input_b_len)                               \
+    PAREN(input_a, input_a_len, input_b, input_b_len,   \
+          (void*) filtering_output_fut,                 \
+          (void*) filtering_scratch)
+
+#define CORRELATE_arm_correlate_opt_q7_INPUT_INTERFACE(  \
+    input_a, input_a_len,                                \
+    input_b, input_b_len)                                \
+    PAREN(input_a, input_a_len, input_b, input_b_len,    \
+          (void*) filtering_output_fut,                  \
+          (void*) filtering_scratch,                     \
+          (void*) filtering_scratch2)
+
+#define CORRELATE_ref_correlate_opt_INPUT_INTERFACE(    \
+    input_a, input_a_len,                               \
+    input_b, input_b_len)                               \
+    PAREN(input_a, input_a_len, input_b, input_b_len,   \
+          (void*) filtering_output_ref,                 \
+          (void*) filtering_scratch)
+
+#define CORRELATE_ref_correlate_opt_q7_INPUT_INTERFACE( \
+    input_a, input_a_len,                               \
+    input_b, input_b_len)                               \
+    PAREN(input_a, input_a_len, input_b, input_b_len,   \
+          (void*) filtering_output_ref,                 \
+          (void*) filtering_scratch,                    \
+          (void*) filtering_scratch2)
+
+#define CORRELATE_arm_correlate_fast_INPUT_INTERFACE(input_a, input_a_len,          \
+                                           input_b, input_b_len)                    \
+    PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_fut)
+
+#define CORRELATE_ref_correlate_fast_INPUT_INTERFACE(input_a, input_a_len,          \
+                                           input_b, input_b_len)                    \
+    PAREN(input_a, input_a_len, input_b, input_b_len, (void*)filtering_output_ref)
+
+#define CORRELATE_arm_correlate_fast_opt_INPUT_INTERFACE(   \
+    input_a, input_a_len,                                   \
+    input_b, input_b_len)                                   \
+    PAREN(input_a, input_a_len, input_b, input_b_len,       \
+          (void*) filtering_output_fut,                     \
+          (void*) filtering_scratch)
+
+#define CORRELATE_ref_correlate_fast_opt_INPUT_INTERFACE(   \
+    input_a, input_a_len,                                   \
+    input_b, input_b_len)                                   \
+    PAREN(input_a, input_a_len, input_b, input_b_len,       \
+          (void*) filtering_output_ref,                     \
+          (void*) filtering_scratch)
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Inputs */
+/*--------------------------------------------------------------------------------*/
+
+/* The following symbols alias the filtering_q31_inputs array:
+ *
+ * - filtering_q15_inputs
+ * - filtering_q7_inputs
+ *
+ * The aliasing conflicts with the instantiation of #ARR_DESC_t structs.
+ *
+ * These macro-level aliases allow the #CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS() macro
+ * to correctly select the filtering_q31_input or filtering_f32_input array,
+ * within a template, by type_suffix.
+ *
+ */
+#define CORRELATE_f32_INPUTS filtering_f32_inputs
+#define CORRELATE_q31_INPUTS filtering_q31_inputs
+#define CORRELATE_q15_INPUTS filtering_q31_inputs
+#define CORRELATE_q7_INPUTS  filtering_q31_inputs
+
+/**
+ *  Defines #ARR_DESC_t objects that wrap existing, type-specific, common
+ *  inputs.
+ */
+#define CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(type_suffix)      \
+    ARR_DESC_DEFINE_USING_ARR(                                  \
+        TYPE_FROM_ABBREV(type_suffix),                          \
+        correlate_input_rand1_##type_suffix,                    \
+        CORRELATE_##type_suffix##_INPUTS,                       \
+        0,                                                      \
+        CORRELATE_MAX_INPUT_ELTS);                              \
+                                                                \
+    ARR_DESC_DEFINE_USING_ARR(                                  \
+        TYPE_FROM_ABBREV(type_suffix),                          \
+        correlate_input_rand2_##type_suffix,                    \
+        CORRELATE_##type_suffix##_INPUTS,                       \
+        1,                                                      \
+        CORRELATE_MAX_INPUT_ELTS)  /* Note the lacking semicolon */
+
+CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(f32);
+CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q31);
+CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q15);
+CORRELATE_DEFINE_RAND_INPUT_ARR_DESCS(q7);
+ARR_DESC_DEFINE(float32_t, correlate_input_zeros, CORRELATE_MAX_INPUT_ELTS, CURLY(0));
+
+/**
+ *  Define Input #ARR_DESC_t arrays by type suffix.
+ *
+ *  Taking inputs in parallel from the 'a' and 'b' arrays yields the following
+ *  test cases (star is correlate):
+ *
+ *  - zero_array   * zero_array
+ *  - zero_array   * random_array
+ *  - random_array * zero_array
+ *  - random_array * different_random_arary
+ */
+#define CORRELATE_DEFINE_ALL_INPUTS(type_suffix)                  \
+    ARR_DESC_DEFINE(ARR_DESC_t *,                                 \
+                    correlate_##type_suffix##_a_inputs,           \
+                    4,                                            \
+                    CURLY(                                        \
+                        &correlate_input_zeros,                   \
+                        &correlate_input_zeros,                   \
+                        &correlate_input_rand1_##type_suffix,     \
+                        &correlate_input_rand1_##type_suffix      \
+                        ));                                       \
+    ARR_DESC_DEFINE(ARR_DESC_t *,                                 \
+                    correlate_##type_suffix##_b_inputs,           \
+                    4,                                            \
+                    CURLY(                                        \
+                        &correlate_input_zeros,                   \
+                        &correlate_input_rand1_##type_suffix,     \
+                        &correlate_input_zeros,                   \
+                        &correlate_input_rand2_##type_suffix      \
+                        )) /* Note the lacking semicolon */
+
+CORRELATE_DEFINE_ALL_INPUTS(f32);
+CORRELATE_DEFINE_ALL_INPUTS(q31);
+CORRELATE_DEFINE_ALL_INPUTS(q15);
+CORRELATE_DEFINE_ALL_INPUTS(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Lengths */
+/*--------------------------------------------------------------------------------*/
+
+/*
+ *  The correlate_lens_a and correlate_lens_b #ARR_DESC_t objects are accessed in parallel
+ *  to provide correlate-length pairs. Taken in parallel they provide the
+ *  following cases:
+ *
+ *  - 1 * 1    : Shortest correlate possible.
+ *  - 1 * 2    : Short correlate , one side is degenerate.
+ *  - 17 * 1   : Medium correlate, one side is degenerate.
+ *  - 15 * MAX : Longest correlate.
+ *  MAX * MAX  : Longest correlate.
+ */
+ARR_DESC_DEFINE(uint32_t,
+                correlate_lens_a,
+                5,
+                CURLY(
+                    1,
+                    1,
+                    17,
+                    15,
+                    CORRELATE_MAX_INPUT_ELTS
+                    ));
+
+ARR_DESC_DEFINE(uint32_t,
+                correlate_lens_b,
+                5,
+                CURLY(
+                    1,
+                    2,
+                    1,
+                    CORRELATE_MAX_INPUT_ELTS,
+                    CORRELATE_MAX_INPUT_ELTS
+                    ));
+
+/*--------------------------------------------------------------------------------*/
+/* Convolution Tests */
+/*--------------------------------------------------------------------------------*/
+
+#define CORRELATE_TEST_TEMPLATE(fut, fut_arg_interface,                                \
+                           ref, ref_arg_interface,                                     \
+                           suffix, output_type)                                        \
+    JTEST_DEFINE_TEST(fut##_tests, fut)                                                \
+    {                                                                                  \
+        TEMPLATE_DO_ARR_DESC(                                                          \
+            input_idx, ARR_DESC_t *, input_ptr, correlate_##suffix##_a_inputs          \
+            ,                                                                          \
+            void * input_a_ptr = input_ptr->data_ptr;                                  \
+            void * input_b_ptr = ARR_DESC_ELT(                                         \
+                ARR_DESC_t *, input_idx,                                               \
+                &(correlate_##suffix##_b_inputs))->data_ptr;                           \
+                                                                                       \
+            TEMPLATE_DO_ARR_DESC(                                                      \
+                correlate_len_idx, uint32_t, correlate_len_a, correlate_lens_a         \
+                ,                                                                      \
+                uint32_t correlate_len_b = ARR_DESC_ELT(                               \
+                    uint32_t, correlate_len_idx, &(correlate_lens_b));                 \
+                                                                                       \
+                /* Display test parameter values */                                    \
+                 JTEST_DUMP_STRF("Input A Length: %d\n"                                \
+                                 "Input B Length: %d\n",                               \
+                                (int)correlate_len_a,                                  \
+                                (int)correlate_len_b);                                 \
+                                                                                       \
+                memset(filtering_output_ref,0,                                         \
+                      (2*CORRELATE_MAX_INPUT_ELTS)*sizeof(output_type));               \
+                memset(filtering_output_fut,0,                                         \
+                      (2*CORRELATE_MAX_INPUT_ELTS)*sizeof(output_type));               \
+                                                                                       \
+                TEST_CALL_FUT_AND_REF(                                                 \
+                    fut, fut_arg_interface(                                            \
+                        input_a_ptr, correlate_len_a, input_b_ptr, correlate_len_b),   \
+                    ref, ref_arg_interface(                                            \
+                        input_a_ptr, correlate_len_a, input_b_ptr, correlate_len_b));  \
+                                                                                       \
+                FILTERING_SNR_COMPARE_INTERFACE(                                       \
+                    correlate_len_a + correlate_len_b - 2,                             \
+                    output_type)));                                                    \
+                                                                                       \
+        return JTEST_TEST_PASSED;                                                      \
+    }
+
+#define CORRELATE_DEFINE_TEST(fn_name, suffix, output_type, test_template)    \
+    test_template(                                                            \
+        arm_##fn_name##_##suffix,                                             \
+        CORRELATE_arm_##fn_name##_INPUT_INTERFACE,                            \
+        ref_##fn_name##_##suffix,                                             \
+        CORRELATE_ref_##fn_name##_INPUT_INTERFACE,                            \
+        suffix,                                                               \
+        output_type                                                           \
+        ) /* Note the lacking semicolon*/
+
+/* Tests on functions without partial outputs */
+CORRELATE_DEFINE_TEST(correlate          , f32, float32_t, CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate          , q31, q31_t    , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate          , q15, q15_t    , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate          , q7 , q7_t     , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate_opt      , q15, q15_t    , CORRELATE_TEST_TEMPLATE);
+
+CORRELATE_TEST_TEMPLATE(
+   arm_correlate_opt_q7,
+   CORRELATE_arm_correlate_opt_q7_INPUT_INTERFACE,
+   ref_correlate_opt_q7,
+   CORRELATE_ref_correlate_opt_q7_INPUT_INTERFACE,
+   q7,
+   q7_t
+   );
+
+CORRELATE_DEFINE_TEST(correlate_fast     , q31, q31_t    , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate_fast     , q15, q15_t    , CORRELATE_TEST_TEMPLATE);
+CORRELATE_DEFINE_TEST(correlate_fast_opt , q15, q15_t    , CORRELATE_TEST_TEMPLATE);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(correlate_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_correlate_f32_tests);
+    JTEST_TEST_CALL(arm_correlate_q31_tests);
+    JTEST_TEST_CALL(arm_correlate_q15_tests);
+    JTEST_TEST_CALL(arm_correlate_q7_tests);
+
+    JTEST_TEST_CALL(arm_correlate_opt_q15_tests);
+    JTEST_TEST_CALL(arm_correlate_opt_q7_tests);
+
+    JTEST_TEST_CALL(arm_correlate_fast_q31_tests);
+    JTEST_TEST_CALL(arm_correlate_fast_q15_tests);
+
+    JTEST_TEST_CALL(arm_correlate_fast_opt_q15_tests);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c

+#include "filtering_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+//must be max(LMS_MAX_BLOCKSIZE*2, FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_L)
+float32_t filtering_output_fut[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_output_ref[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_output_f32_fut[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_output_f32_ref[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_input_lms[LMS_MAX_BLOCKSIZE*2] = {0};
+float32_t filtering_pState[LMS_MAX_BLOCKSIZE + FILTERING_MAX_NUMTAPS] = {0};
+float32_t filtering_scratch[FILTERING_MAX_BLOCKSIZE * 3] = {0};
+float32_t filtering_scratch2[FILTERING_MAX_BLOCKSIZE * 3] = {0};
+float32_t filtering_coeffs_lms[FILTERING_MAX_NUMTAPS];
+
+const q31_t filtering_q31_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] =
+{
+    0xC14A5524, 0xCCABDA17, 0xAD6F5B56, 0xFDAFCE3B, 0xA9B226EB,
+    0x41F6F6A, 0xA5CE38BF, 0x3A978AFA, 0xBA44B82A, 0x855C0F8,
+    0x3D060524, 0x93D5E570, 0x97D7791D, 0xFFE0C38C, 0x26749841,
+    0xC0A6EE54, 0x218EC386, 0x39FF3726, 0x8DC1F7CA, 0x702F2CF5,
+    0xC1142FF1, 0xEC1476AB, 0x15F640DD, 0xE62CCE49, 0x3805DE7E,
+    0xF70871FE, 0xCF8BD360, 0x8D19A8A0, 0xD764F821, 0xA58558CF,
+    0x8C0CE04D, 0x50A46C19, 0x66D2370D, 0x50FA359A, 0xB646AE24,
+    0x6CE00F5C, 0xE6D48948, 0xB55BD831, 0x3B72950A, 0x9EB69530,
+    0x73394127, 0x773FA6F4, 0x9805A980, 0x838DE587, 0x9CF597F4,
+    0xA2AD1691, 0xFA81A473, 0x7CDC7D7F, 0x4A5190D0, 0xED895BB9,
+    0x8FD60F35, 0x1A21D530, 0xA0EB6DDA, 0xBDE6A516, 0x2501A3E1,
+    0x5ED893C8, 0xE1E175B1, 0xACBBB2F3, 0xED350907, 0xDB140D7E,
+    0xEEAE272D, 0xBE229841, 0xC18BFB88, 0xA6BB9B80, 0xBCF090E4,
+    0x24DB166C, 0xF9AB7E42, 0x62DF28D1, 0xC7004665, 0xE3F56FC6,
+    0x419E0C75, 0x46BE9F38, 0x2432B9B2, 0x758D83E0, 0xDCE12926,
+    0x3F57CB74, 0x1F4458E2, 0xF1DD639, 0x83A1FB49, 0x173AFC76,
+    0x86EF7531, 0x48D32F34, 0x7D3E3063, 0x8F2FB549, 0x5C314C9,
+    0x18CBEB6D, 0xA6F8B697, 0x447B9E9C, 0x2E32BA33, 0xD074D715,
+    0x81ACD746, 0xE55A4E04, 0x4891860F, 0x1DA3EB4F, 0xE0E6A27F,
+    0x20BFDEB4, 0xD0B3A25B, 0x40C10544, 0xC15656C, 0x15405EAE,
+    0x9858E3E1, 0xA36A9C4E, 0x88BD21F9, 0xAACF7A68, 0x773665E5,
+    0xCEDFDF66, 0x617A9610, 0x524FC968, 0xC2D086CD, 0x5F008079,
+    0x24DCA447, 0x6A4F5599, 0xB706CD4A, 0x1DE70608, 0xA33A2EE5,
+    0x137E488E, 0x98061B7B, 0x4079D69D, 0xA4A897D5, 0xC4CEC8F5,
+    0xD75F7883, 0x22406802, 0xF1AD70BB, 0x9D4ADD79, 0xBCBC7CE4,
+    0xB358C0D8, 0x85792E47, 0xA7ADAC05, 0x3D19EEAB, 0x331AC0AF,
+    0x33035831, 0x13D93987, 0xFC542094, 0x845F317E, 0xDDC4BF8B,
+    0x1379E50C, 0x5C20193F, 0xFDD58298, 0x9D482B82, 0x4A6BE062,
+    0xDC8A757B, 0x272917C1, 0x90E1EFBC, 0x355AD882, 0xE6F8EA35,
+    0x604555A1, 0x7DFFFBB, 0xF58AE216, 0x9A11B463, 0xD3541BAD,
+    0xA1576756, 0x483BED8D, 0x1F05AFCC, 0xCEA63DFB, 0x55B84677,
+    0xFB2E04F2, 0x787AF96C, 0x84A12CD3, 0x460A9BD, 0x9DB22DD8,
+    0x1A8C7F28, 0x861E452E, 0x932D3F78, 0x7652D852, 0x73357BBA,
+    0xEBBB0A58, 0x62536AFA, 0x3F6B65EF, 0x6DC57B58, 0x9EB798CE,
+    0xE6B0A740, 0xDFF68B47, 0x3247FB8F, 0xFFF3D302, 0xA9FD3E40,
+    0x475A43D1, 0x6FF9528A, 0x2018A09D, 0x47E0F9C9, 0x4CF5F6D3,
+    0x2807CE34, 0xDD6FD8ED, 0x234045D1, 0x51CEB5F9, 0x25297896,
+    0x6443A0FE, 0x8F4449A9, 0xD4C3E1C6, 0xF01D52F1, 0x4E09C820,
+    0xF18F0810, 0xE1548689, 0xF9DE5A1F, 0x5286DC23, 0x48AC3A4B,
+    0xEA0C1BE0, 0xA1B785DB, 0x7086465D, 0x1CC10929, 0x1E1D716E,
+    0xED231D4C, 0x2049D108, 0xB8FF9971, 0x949CF8D4, 0x441F1E8B,
+    0xC3D95372, 0x69C324B4, 0xA10BFDC9, 0xC781DE78, 0x82476137,
+    0xE163DDF, 0x390DEEC2, 0xAF68CE5B, 0x8E680ABD, 0x8223A615,
+    0x92593380, 0x7B1465FE, 0x865AE957, 0x930F53EB, 0xED772EF7,
+    0x10E916B6, 0xE3BCFA68, 0x2ACB80BB, 0xE51C5590, 0x994714B5,
+    0xF30984EE, 0x59BBE1B4, 0xB4867DBC, 0xB91C706C, 0xBC16C218,
+    0xA8931CD0, 0x129A66AB, 0x13171F4D, 0x62882872, 0x4B167FD4,
+    0xE6902F4C, 0xFA794932, 0xD4B152C, 0xB0856EA9, 0x39466D55,
+    0x3669E451, 0x8F5B9E8C, 0x877A3C6A, 0x51B956B4, 0x367EAD2A,
+    0x9D2C662A, 0x78FB6880, 0x4E6D40B6, 0x4070EFDC, 0x4DF9679C,
+    0x20306EDB, 0xE381AAE7, 0xA55DA748, 0x9B8B617B, 0x3E036FAD,
+    0x84E4C4A7, 0xD5A3F517, 0x669BA988, 0x98FDDE8C, 0x67BD85CE,
+    0x34BBB46C, 0x76994800, 0x85B9D8B6, 0x6DFA2FEF, 0x205DB5C,
+    0x9F843C4C, 0x72721B52, 0x73EF6B86, 0x5FB98B61, 0xC323DDAC,
+    0x31D424B4, 0xF68C0D7E, 0x162FAF9D, 0x7B2A7A99, 0xF9392693,
+    0xC42D12C0, 0x8692A73E, 0xD9A1EE80, 0xDD956856, 0x44E7BDAC,
+    0x8D874532, 0x5F5C9DD0, 0x5D167858, 0x8559FEA2, 0x9D821476,
+    0xD9654ED2, 0x594C0DC7, 0x1A87B506, 0x3F693200, 0x7A651AB5,
+    0xA0CCBC8A, 0x9F9E662C, 0x78EF631, 0x2A09DA0, 0xB088C72F,
+    0x92EE0D42, 0x360DCD5F, 0xF333FE48, 0x8D63CC06, 0x233A8ACB,
+    0x706651ED, 0x7AA5C079, 0x262239D1, 0x3EBBEBB6, 0xA25A4F3D,
+    0x32581A06, 0x6E6FD780, 0x5773F7C7, 0x75ED1DDC, 0x90DF2D15,
+    0xBC79A9BC, 0xB7175917, 0x354E381C, 0x762AADD7, 0xF643DAC1,
+    0xF3BBF49E, 0xD2FECE7E, 0x6C8140F4, 0xD7694875, 0x92D30822,
+    0xC742A7CF, 0xB792ED98, 0x121CFE24, 0xA04E1EE7, 0x58CE268,
+    0x215A080, 0x316CB323, 0xFAB14A31, 0xE1C13C03, 0xFD8EF4F1,
+    0xF3F446D0, 0x6C6CEA0A, 0xBBFDF9FB, 0x67242969, 0xBE55A4EB,
+    0x8FF5534, 0x52F0DF1C, 0x9710ADE3, 0xD40F4A21, 0x7984E8E7,
+    0x419545EB, 0x993F7880, 0xAB246B20, 0x408AABC4, 0xCBF6EA49,
+    0xC0894C55, 0x4CAA6398, 0xA47856E9, 0xAF2AE47D, 0x22F55D33,
+    0xF0D37915, 0xD0634C72, 0xD983671, 0x2BCC5AF8, 0x9A77D48,
+    0xC11B5CFA, 0xF107CD7E, 0x3A6B3593, 0xE1425F05, 0x6271812A,
+    0x5B838310, 0xBD8418CA, 0x10A58792, 0x239F7137, 0xA13D5071,
+    0x7F9930D4, 0xA462664F, 0x54180F8E, 0x291585BA, 0xE586B87A,
+    0x144B2C12, 0x98E425C7, 0xBAA4B373, 0x18F0D03C, 0x99462AC0,
+    0xD8B4D2EF, 0x72473895, 0xA6BF5435, 0xEDAD53B, 0xE0912FA6,
+    0x5C33F331, 0x3D93CD7, 0x4D03D752, 0x20699929, 0xB89962F9,
+    0x36E781E9, 0xF58B642C, 0x5FCA69E3, 0x5960A7F4, 0xAD5AAFD0,
+    0xDF18324A, 0x3DB1E5AA, 0x76BA3876, 0x1BC29AF6, 0xBCC18841,
+    0x73A60174, 0x625BFF58, 0x67C57724, 0x4458E53C, 0xE157B095,
+    0x2B370837, 0x83DF6CE3, 0xDD08EEFA, 0x3F52A7C2, 0x191B4785,
+    0x60843D82, 0xB0DE11F1, 0x105EA26C, 0x6E1C7AA2, 0x47AADD14,
+    0xB6676D03, 0x3B8D4DF6, 0x737A694, 0x409521DC, 0x744206A,
+    0xC722023F, 0x2BE4EAD5, 0x63E11D76, 0xCA4A09AB, 0x5CF2D2B9,
+    0x31586916, 0xCDFD7D84, 0xB203F634, 0xAD7329D4, 0xC524582F,
+    0x2E53E6C1, 0xBB0E019B, 0xB8538C6A, 0x6A2542D, 0x8A6A00E5,
+    0x119725CC, 0x5406D347, 0x1B6FFAF1, 0xECCF71F1, 0x981117F2,
+    0x7167CA76, 0x74F4B880, 0x77A55F47, 0x59EADB62, 0x4A331D95,
+    0xBCBBA76F, 0xA45C4D50, 0xC718D5, 0x87CE05D1, 0x60D47AD5,
+    0xA5CA9C40, 0xB0061766, 0xE69B39DF, 0xBD5F1320, 0x9930EAD3,
+    0xA8B38325, 0x8DD090F, 0x6A6EEF37, 0x2DF16F66, 0xAB514C7E,
+    0x31109C58, 0xFD48C7FC, 0x515341CA, 0x77AB8EA6, 0x41328DAF,
+    0xBAF8D31E, 0xA4B31611, 0xED37F331, 0x7A832A22, 0xA22591C7,
+    0x722D1F89, 0x3B19CF18, 0x261B8A4D, 0xC3F6F6DB, 0xCF8CED61,
+    0x990FA250, 0xA02E72A9, 0x560DCEA2, 0xB08E67B4, 0x3674E663,
+    0x97CC3852, 0xA7EB2EAC, 0xFFDE0AA8, 0xA64719A, 0x23269EDD,
+    0x3C0B339E, 0x86284D40, 0x48D82ECB, 0xA4D4CCF8, 0x43631B91,
+    0x4BF0C248, 0xB6497B9B, 0x6827BC58, 0xE30B7AF9, 0xA0CCBF26,
+    0x6C3B7B71, 0xD744B3ED, 0xFA25D2F6, 0x4CDE642D, 0xD65B8142,
+    0xA6F9207F, 0xE7A207BE, 0xDB506684, 0x44DA4780, 0x9175EA0C,
+    0x156104AF, 0x4155E1B0, 0x6E3A6886, 0x9DBA1EA2, 0x5423D9C8,
+    0xCC024E22, 0x758F852A, 0x1DD6395, 0x2D19CBAD, 0xE164F5A1,
+    0xC2084602, 0x89C274AD, 0x13CB5562, 0xD7FE2D5B, 0xE07A4EE5,
+    0x1672BA91, 0x4F624CCF, 0x2E5EA4A3, 0x28FEEFAF, 0xBDDA6EF4,
+    0x32AFD40C, 0x99A5FB3B, 0xDD1D73A3, 0xA342CB3E, 0xA78445F5,
+    0x53979C3B, 0x427D7943, 0x5221B58C, 0xA6CE9A5E, 0xFB50ECA4,
+    0xBB86E36E, 0x60839F6D, 0xC5E1C2F3, 0xA1B7FB04, 0xFBB65E0C,
+    0x78B80F5E, 0xFD8D972B, 0x3BF3BA90, 0x2D572D9, 0x2B5BC920,
+    0xB6A0DE01, 0xD274D306, 0xC7C6C855, 0x9CAA669B, 0xB04AA641,
+    0x4D6B1760, 0x3E17ED79, 0xD23241B0, 0xA4A6F957, 0xCBDE76AF,
+    0x4E5F9493, 0x4C215DA5, 0x33A052B, 0x1A4D80C2, 0x40AEEBCA,
+    0x390D106B, 0xE9E8E018, 0x5AF3D6CF, 0xE35E1D4, 0xC4FB1C6,
+    0x14B6299B, 0x8D2E25F0, 0xCCBF932A, 0xC5AC18B6, 0x2227567D,
+    0x86B5CE2F, 0x26344534, 0x22C515EC, 0x2442B70D, 0xEC3721C6,
+    0x34EF687D, 0x9C06323A, 0xEAF3EA60, 0x60396F52, 0xEAE78AA1,
+    0xC9D06CBC, 0x6F95F6C8, 0x584CC258, 0xBA9A27BB, 0x66DF8D47,
+    0x9D4804EA, 0x57DD9E67, 0xF89C7895, 0xF5336111, 0x25C122C8,
+    0x62742114, 0xCFBF6D26, 0xBF9F6482, 0xE6F02CD9, 0x11083202,
+    0xC99E2618, 0x7EBC9351, 0x440112F1, 0xC9DFFBC1, 0x3BF4DC25,
+    0xB1BA7FA0, 0x61AF9AED, 0x6B1F7D29, 0xAD865294, 0xE3E01129,
+    0x7E9E77A5, 0x100435D7, 0x9FE3A71, 0x88597C81, 0x722849FA,
+    0x31C5A0AF, 0xFBA178DC, 0x7F102D31, 0x5CA07864, 0x950E6F98,
+    0x82C34882, 0x5D041F11, 0x8C613C57, 0xD398CFD1, 0x426F38AD,
+    0x5599AB1D, 0xFAFA078D, 0xAB25B413, 0xD94B32CF, 0xB288FE38,
+    0x2893BB46, 0x9A0B4168, 0xA91BCA94, 0x653A5E8D, 0x2174EBBE,
+    0xDEFE6415, 0x30DA429C, 0xD0C5E40C, 0xB4719AA4, 0xD29CE7A6,
+    0x905957CD, 0xCD287499, 0x83CA0AA7, 0xA8385832, 0x25A0CA02,
+    0xC20D47A4, 0xB562F556, 0x4BC19E4C, 0xD9E215C7, 0x27E838B4,
+    0xC58612F4, 0xA2827F6F, 0xC49DCDBA, 0x679B7362, 0x4E495845,
+    0xCFD2F0D1, 0x395E76A0, 0x375A655E, 0x92E2058F, 0x73F9F0CA,
+    0x61EFF3B3, 0x51FFD362, 0xE7410345, 0x7FDA8B3B, 0xA219E2E8,
+    0x17ABE543, 0x26557412, 0x4B30084D, 0xA68E191D, 0xFE0D93DF,
+    0x73EF127D, 0x4DECDDB1, 0x77FAF45F, 0xD6002898, 0x92DD0A40,
+    0x157F6DDF, 0xC2A55F8E, 0x4359F924, 0xFB630C3F, 0x338B6B58,
+    0xB2945F75, 0x4FA23A0E, 0x836EB8C0, 0xB3B18FD, 0x86114337,
+    0x24668ACB, 0x99BB82F0, 0x924C8A47, 0xBA959701, 0x81155ABF,
+    0x8C612D71, 0x36074CA7, 0xD1668C41, 0xE35F58C7, 0x7FC2802D,
+    0x8E6A7CF3, 0x65B07D07, 0x815F6A6B, 0x791BF0DD, 0x6E47D719,
+    0xC24394C7, 0xE84A6EB, 0xF194AFEE, 0x464A2F52, 0x677579FD,
+    0xEBA775AE, 0x1F6EEFF, 0x9A795237, 0x78D9D45F, 0x9D0B344D,
+    0xBBD34AB7, 0x2F85B12A, 0x16C5C2AD, 0x3990985D, 0x88DF3351,
+    0x82811AA5, 0x6D351F41, 0x4066A69D, 0x86B660BF, 0x6EDB4768,
+    0xDDD78CF0, 0xB5D74F6E, 0xE89E220C, 0x91439687, 0x947CC9C9,
+    0x3857E2BD, 0x302F8AE4, 0x1DABE7F8, 0x4832D6C9, 0x37D58FCB,
+    0x4EA8A711, 0xCD7BAC98, 0x19DBF8BC, 0xD8DE8DC2, 0xEAFF7E7B,
+    0xB7629C93, 0x792C6E19, 0xF7009192, 0xFF88439D, 0x2E196A66,
+    0xEC71B78C, 0xEAF4BB3A, 0x7C16225E, 0x668F337, 0xCBEE1608,
+    0x6D5B5552, 0x345DC590, 0x681209CC, 0x7B24A819, 0xD08A1416,
+    0x99888FE3, 0x9FC7288A, 0x24BD8502, 0xEA1D9678, 0x20EECA0,
+    0x59BEA057, 0x5ADE91EB, 0xDEA8E49D, 0xFA200E6F, 0x9149C81D,
+    0xF2281E93, 0x8A5B0451, 0x67312D58, 0xE3B849F1, 0xD2217960,
+    0x7CDF59F3, 0x33C775C0, 0x9EBA8799, 0x7DF9506, 0xB4E96110,
+    0xB8FCF3E3, 0xDEA059B2, 0x8229B6EA, 0x316486F6, 0x43919185,
+    0x6C0D90F3, 0x1C6F3DF8, 0x38DB92A9, 0x5CD41244, 0x2C9F0A7B,
+    0xDF4A315F, 0xF7CE9C66, 0x4C800860, 0x318D53E0, 0xF105C20D,
+    0xD753E1F2, 0x750810BA, 0xA17ECCA5, 0x2010140, 0x4D884763,
+    0xC2BB0DA7, 0xB2D5BA74, 0x141CECD4, 0x887FDFC3, 0xC64B53,
+    0x2D2A85F6, 0x15532B45, 0x5D5CBCE1, 0xBEB9A16A, 0xA214611B,
+    0x9FC5AC5F, 0x11AE5DD7, 0xA0B9A5A9, 0xFC648AF4, 0x740009AC,
+    0xED0E0321, 0xB8E6A61, 0x8910C544, 0xC74F26C8, 0x9525CCF3,
+    0xB41AEB59, 0xE61984CE, 0x598B2197, 0xA412E59D, 0xE1976DD4,
+    0xB29BBE16, 0x88FD9FB0, 0xB04006F3, 0xB45E309, 0xD5CC15F1,
+    0xD9DAF630, 0xDC809335, 0x803ED52, 0xB537F5A5, 0xA994F6EB,
+    0xF5288568, 0xF66FD264, 0x2EA2B3A6, 0x647619F3, 0xFFB38C7A,
+    0x1BC03B9, 0xB6BC3061, 0xBF30596E, 0xBE2AD27B, 0x8AC04220,
+    0x641979A3, 0x9ECCBB89, 0xA144FBC1, 0x4E8FAE26, 0x8C5A9D90,
+    0x299ED467, 0xD7C9C7E3, 0x1D4865ED, 0x76F31C3D, 0xCEE81CDF,
+    0xB479195E, 0x6FFB3AE1, 0xDC8A398, 0x300F7364, 0xC7940AFA,
+    0x3B85BE3E, 0xD98CC40D, 0xA24A3D89, 0x3A674204, 0x22888A38,
+    0x2E77F2D, 0xA2841C9C, 0xCF0689C3, 0x9FE98922, 0x89335017,
+    0x2D6B69A7, 0xFEDB63F9, 0x899AF4EF, 0x9F9F9B40, 0xA4BE97E8,
+    0xA51DAF7A, 0x16AC50D3, 0xA8D7ED6, 0xED193443, 0x7615EF1B,
+    0xB0DF6A4E, 0x64FFE794, 0xE3DB2C9A, 0x7435B022, 0x556E825C,
+    0x23802AF9, 0xC25098A4, 0xE75A18BB, 0x70B2A7B9, 0x7FB81BF,
+    0x63EF910, 0x6C669591, 0x6574DD2B, 0xCF6E379D, 0xD2B3AFAC,
+    0x1E6A1101, 0x1DE22385, 0x2338191F, 0xC69704B6, 0xCBABC599,
+    0x54EB4809, 0x7839BE6D, 0xD50017DD, 0x39B1A0E1, 0x288D52D3,
+    0x2D52668C, 0x20D22A68, 0x4E1207D1, 0x3FCC0EFE, 0x47F3FE64,
+    0x25177A90, 0xB4BFDD4D, 0xDA8DBDCE, 0x6F7275A8, 0x6BEAA655,
+    0xAA1810FC, 0xE4DB593A, 0x8A4D4BC0, 0x2C402E93, 0xF1C0F7F9,
+    0x6F0CC577, 0x70412414, 0x752F9DC1, 0xD82E38EA, 0xAC455F7B,
+    0x4DCD4EDB, 0x92BC2696, 0xFB03F135, 0x4FCA1F8C, 0xBD5E75F6,
+    0x502F41B0, 0x3616D3F1, 0x2E5B8E31, 0x2026EB19, 0x57E783D7,
+    0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48,
+    0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED,
+    0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F,
+    0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB,
+    0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94,
+    0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11,
+    0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x73D63FED, 0xE36E9F5E,
+    0x8AC1DA0E, 0x3F3DB3EB, 0x738326EA, 0x35C366B1, 0xCD476E86,
+    0x82F6B208, 0xF11A9FC1, 0x426AC396, 0x7E4D1B93, 0x75E4EDB7,
+    0xAF3C44A7, 0x51A5EF5C, 0xFAD2463D, 0x8A5639CA, 0xC995AC78,
+    0xCC4BE4F6, 0x3AFE7F8D, 0x66993D04, 0x4386FF37, 0xCBC1C6C2,
+    0x55A8F5EC, 0xE81A9A75, 0x30A67E1B, 0x4A4A7D0C, 0x20F7F993,
+    0x1891805, 0x738976AD, 0xD426E7D6, 0x3C5CEEBF, 0x4499187F,
+    0xABF17C97, 0x447C317F, 0x68D8419C, 0x7AAB6456, 0x421BCF29,
+    0xF6740F9C, 0x8916BB8D, 0x3D72AAB, 0x9AD54DD7, 0x7549C6EE,
+    0x7317342B, 0xA18546D4, 0x1056BDA7, 0x54BBCCCE, 0x8CE63E46,
+    0x5D146234, 0x33BE6C63, 0xB250C4E5, 0x89D72335, 0x87C36BA,
+    0xB65530CC, 0x2DFAC48C, 0x1663D16F, 0x59B80AA, 0x950274EA,
+    0x92532D4A, 0x3CEF802D, 0x492FBDA5, 0xA63A2574, 0xEF8005C2,
+    0x94A18651, 0xAF627ABA, 0x6829B238, 0xA698F646, 0xD2598516,
+    0x10144D36, 0xD9B1D1B9, 0xAB2ACF05, 0x5395B699, 0xA7851C75,
+    0x1806C6F3, 0xAE970306, 0x3284B145, 0x98F4FE8F, 0xECDD35CC,
+    0xDDC1EE0E, 0xC4848865, 0x925826BD, 0x4078BE39, 0x68A8561A,
+    0x323045DC, 0xA933B37F, 0xBA2AEE2E, 0x4F24F65D, 0x349EE246,
+    0xF97B9D0E, 0x46DC5759, 0x4529F425, 0x80D17B42, 0x8E16F709,
+    0x1B42206A, 0x4934A526, 0x391BB6DE, 0xB52EF45C, 0x26C30290,
+    0xCBA23CAA, 0xA501A8C3, 0xD922C4F8, 0xE8824E53, 0x6F4255DC,
+    0x5960B544, 0x58BC69D6, 0xCA936323, 0xFDDF053C, 0xC2E002D6,
+    0x7D750755, 0x8A3F9CD1, 0x35F8F6F8, 0xFB7BD154, 0x65CFF94F,
+    0x390A58DD, 0xD97C4093, 0x501CA2A3, 0x8EA5DEBC, 0xCA93461F,
+    0xE02D984C, 0x126F8517, 0x39FDD887, 0x46241AE9, 0x777E854D,
+    0xE2B36349, 0x58E3FA9F, 0x971DEF1E, 0x8E156228, 0xC0E14E9,
+    0xA9A01BE6, 0xB318C990, 0x971680D6, 0xA1F359CE, 0x487E23F4,
+    0x7DE465B0, 0x4E4C905E, 0x2A652959, 0x116FF167, 0x5C74AAB9,
+    0x467BBE00, 0x4703ABA3, 0x1F776B9C, 0xE2570A84, 0xFEC7DB48,
+    0x1BD5012, 0xFD0A2D5D, 0x7FCC29F2, 0x291304B6, 0x99D5D8ED,
+    0xC7551C8, 0xFD12F38F, 0xBADE8892, 0xDF749997, 0xA5DAE2F,
+    0x2B9FA269, 0x5C13CFED, 0x15E9A399, 0x54437F4E, 0xA72DB2AB,
+    0x56186AA1, 0xFE4DB55C, 0xA34D7836, 0x2A879760, 0xC63FA94,
+    0xAC18B207, 0x5FC78B3, 0x7F10621E, 0xA769E6B2, 0xEC9F4A11,
+    0xCE3F982C, 0x62BA2EF5, 0xA5F239CD, 0x4FEFC920, 0x28DF4EB8,
+    0x29EBF45A, 0x1E350CF6
+ };
+
+/* The source data is random across the q31_t range. Accessing it by word should
+   remain random. */
+const q15_t * filtering_q15_inputs = (q15_t *) filtering_q31_inputs;
+const q7_t * filtering_q7_inputs = (q7_t *) filtering_q31_inputs;
+
+const float32_t filtering_f32_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] =
+{
+    43.0264275639  , -17.0525215570 , -94.8488973910 , -8.1924989580  , 7.2830326091   , 66.8368719314  , 33.9778190671  , 117.8652289772 ,
+    -129.6077797465, -14.6420815368 , 18.0239223278  , 20.6760530292  , 55.0375037651  , 1.8674609862   , -85.6534302408 , -33.5750364909 ,
+    29.2110949614  , 110.4727049460 , -94.1914619387 , -1.4084169343  , 83.5181653041  , 47.3073514127  , -13.3420621181 , 30.3389699104  ,
+    12.1188124277  , 100.9730921941 , -114.0146362390, -77.5823200409 , 37.2019034618  , 40.0026301128  , -58.3387276630 , -34.9472398600 ,
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+    53.9279617551  , -16.9017895140 , -70.1527553166 , -79.6367897992 , 109.3728271017 , -129.2214826835, -53.4644539730 , -51.5654458993 ,
+    17.6062148433  , 3.5090251835   , 74.2615941204  , -109.3431097845, 40.1403465151  , 28.8714561280  , 94.0868659302  , -19.0047033845 ,
+    -60.0967410050 , -19.0998457619 , -67.2027075128 , 72.0711434846  , -17.8737851232 , 123.7050551274 , 132.6331504104 , 25.5018761009  ,
+    -36.7817189239 , -29.1580893235 , -6.5848563828  , 90.2868948516  , -35.7017258498 , -68.5675432955 , -52.4888589786 , 47.1377730021  ,
+    -7.4546621940  , -52.0657517138 , -49.0404829633 , -114.6910280126, -117.6819819437, -32.7856729408 , 31.8232065591  , 12.1192973039  ,
+    35.2678513420  , -1.0336778293  , 30.7021249679  , 127.0442906046 , -84.8457819393 , 28.9862843096  , -47.3524701726 , -126.1094998460,
+    -2.9700276582  , -2.4956545870  , -53.8624121141 , -85.2114117637 , 76.9057985618  , 137.1205201755 , -19.0830817212 , 14.3407526579  ,
+    -56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090, 0.3487447576   , 33.4499716730  , 34.7126257844  , -9.3307383323  ,
+    27.2996276947  , 10.8765676134  , -91.1032360444 , -90.9584216222 , 1.6981490570   , 96.8557438791  , 56.7726390913  , -44.3246449237 ,
+    52.3260643361  , 21.5551140465  , 27.4535327381  , 2.0072717479   , 7.4823125629   , 77.1185863870  , 16.1372262663  , -10.7206012957 ,
+    66.8830091413  , 49.3523828287  , 54.0855375598  , 30.8570349345  , -10.9255375390 , 62.3910624674  , 30.9238561381  , 0.3352881853   ,
+    72.1022806197  , -28.8319885008 , 23.3335288806  , 46.8999035980  , -67.0984424822 , -164.7917209112, 42.5767681360  , -92.4668227688 ,
+    43.8491734282  , -17.1126540408 , 37.4819594334  , 69.0774409673  , -39.3530526854 , -14.0693747124 , -60.2520781215 , -80.3860105519 ,
+    32.6689956840  , 15.3393042576  , -18.5529761307 , 97.3942151573  , -4.4462855745  , 13.7614349817  , 158.3358780719 , -44.7258299667 ,
+    -17.7741912819 , 116.5136962268 , -33.6261057820 , 22.8344441288  , -155.1423976144, 5.7070117893   , -22.7906543902 , -45.0633909283 ,
+    -13.9329987929 , -66.0848932507 , 1.1383038109   , 123.8386958483 , 67.6662401589  , 45.9152963554  , -27.4397697462 , 97.9596747354  ,
+    -6.3544655181  , 29.0832146722  , 96.3468162499  , 32.4535976137  , -91.0650399301 , 2.7293262791   , 70.7853483111  , -92.3655274571 ,
+    69.0359217256  , 83.1530567979  , 35.8375091111  , 7.3393552348   , -95.1770165365 , 76.4905790891  , 55.6253140577  , -29.5315327050 ,
+    -16.5935468750 , 20.4574192236  , -88.7897972666 , -38.6285080386 , 53.3203422726  , 98.5991486746  , 122.7305462474 , 67.7902817187  ,
+    5.1764117389   , 5.0632821624   , 21.9288789574  , -78.3140512638 , -21.2069682335 , 23.6342010925  , 34.4445769455  , 59.1346766615  ,
+    28.9978778000  , 39.8121180845  , -17.1650033520 , -56.9174900874 , 17.8157086148  , -112.8801457350, -122.4019040408, 140.8669393157 ,
+    -65.4664329639 , 40.6952775518  , 32.7260891658  , -43.2565155866 , 19.3945751928  , -20.1815002000 , -67.6601711640 , -18.1921178207 ,
+    -35.6802153684 , -19.6571455162
+};
+
+const float64_t filtering_f64_inputs[FILTERING_MAX_BLOCKSIZE * FILTERING_MAX_M + FILTERING_MAX_NUMTAPS] =
+{
+    43.0264275639  , -17.0525215570 , -94.8488973910 , -8.1924989580  , 7.2830326091   , 66.8368719314  , 33.9778190671  , 117.8652289772 ,
+    -129.6077797465, -14.6420815368 , 18.0239223278  , 20.6760530292  , 55.0375037651  , 1.8674609862   , -85.6534302408 , -33.5750364909 ,
+    29.2110949614  , 110.4727049460 , -94.1914619387 , -1.4084169343  , 83.5181653041  , 47.3073514127  , -13.3420621181 , 30.3389699104  ,
+    12.1188124277  , 100.9730921941 , -114.0146362390, -77.5823200409 , 37.2019034618  , 40.0026301128  , -58.3387276630 , -34.9472398600 ,
+    -5.1169678311  , -87.7660091118 , -150.5888601131, 56.0349370503  , 50.2168884079  , -74.2313236767 , 22.3648603560  , -6.8676387051  ,
+    74.8957303680  , -90.1292012823 , -55.1436241586 , -66.6732976100 , -6.7918147615  , 7.7612697081   , 35.7892605979  , -20.0470508830 ,
+    41.8369017546  , -143.7378056984, -41.9127158600 , -108.3531841158, -57.1917422289 , -124.2808828105, 38.9316388820  , -77.9212517405 ,
+    37.1990818377  , -28.9545952748 , -155.6371057564, 45.8088886393  , 36.2537018275  , -6.5727656016  , -104.2070491921, 45.5583813729  ,
+    -19.7674717059 , -80.4802190947 , -1.4444563441  , -42.2142256438 , 36.6546339194  , -57.0866498590 , 44.4677067511  , 65.7285753407  ,
+    -103.8158864647, 25.4348723711  , -153.5419639389, 39.3608409474  , 49.1658103436  , 79.5570602275  , 75.2944095996  , 58.9394700746  ,
+    -53.1018534392 , 33.4172444014  , 35.6224682287  , -64.4353396418 , -125.8464291251, -47.6072111617 , -26.2177687594 , -12.0061322096 ,
+    -17.7887967585 , -28.2926175090 , -62.0691715749 , 40.5098573604  , -191.1123732593, 119.6750713043 , 19.6182375803  , -26.7615252921 ,
+    2.2957847015   , -108.3436451287, -50.5906164995 , -5.6360985100  , -11.6772204201 , -84.2765293757 , -60.9317810068 , 82.0446350218  ,
+    -70.2048296348 , 72.8738253222  , 60.2450218115  , 114.2741231228 , 46.8180775285  , 6.9915412654   , -8.9909197429  , -78.9165936808 ,
+    66.4731535459  , -68.4235455651 , -79.8254597080 , -10.6308477115 , -62.6161569330 , -55.7744410292 , -11.8408366528 , 98.1034940997  ,
+    35.8213741877  , -54.4694482732 , 86.9631830044  , -53.0343838122 , -47.4898642865 , -47.2010929590 , -31.3312639685 , -23.0908245172 ,
+    12.0258009869  , -5.1098204703  , -9.8420230737  , -107.3328761158, 44.6810431959  , -17.9083820345 , -60.9753512872 , -7.5915088994  ,
+    17.2250813329  , 57.9176125648  , 124.3004161362 , -63.1950908493 , 120.5788885640 , -44.1734238117 , -91.7408095116 , -43.5696066595 ,
+    -49.9560710099 , -167.8513443296, -70.9437505499 , -46.4109705355 , -64.2264526456 , -13.9995803916 , -100.9548186356, 9.9101010575   ,
+    -50.0615130815 , -55.7590145012 , -60.3195153388 , 61.7913378549  , -102.0850899209, 53.2360193126  , -25.8997883369 , 75.1445512333  ,
+    -113.8148602310, 17.8027281119  , -19.5006822722 , -44.2169628471 , 107.5017084384 , -113.7909124666, -43.9735396033 , 7.6880981388   ,
+    46.7384653508  , 9.9047443751   , 81.8646964362  , 132.3812863877 , -95.6959050236 , -68.5015813484 , 65.8586404494  , 18.5039353889  ,
+    -30.1786166621 , -90.3098515667 , -22.9356228552 , -20.5778272423 , -2.2127786675  , -35.4418447703 , -51.8722915974 , -107.9024439078,
+    -51.5940748232 , -51.7463262677 , 74.2795485984  , 94.2205022462  , 9.7016384049   , -47.3556083155 , -36.7822314478 , -151.6455525363,
+    -15.7183814485 , 78.2063383182  , 0.1516414969   , 37.9304181609  , 20.6185902740  , -22.2164106778 , 6.1160554677   , 2.4061326953   ,
+    -111.6681824598, -60.0858917090 , 75.1698614693  , -76.5787410444 , 28.3391655715  , -2.4946186443  , -68.0378899682 , 104.0893199171 ,
+    -51.8319647254 , 38.8521710524  , 75.9114239564  , 73.9206172905  , -103.2533029987, 6.9002718274   , -36.6346436319 , -25.1990926265 ,
+    1.5852145953   , -50.6438436795 , 21.5018844428  , -151.9305562846, -51.7326681814 , 21.4475994143  , 42.2564011921  , -74.0520586926 ,
+    49.7370635809  , -13.2957534126 , 36.6746826778  , -31.7005492589 , 148.4894964268 , 79.7890632353  , 16.8856024809  , 16.1690460177  ,
+    39.2665169484  , 117.2461167794 , -37.4827984831 , -47.8387803604 , -95.7025286193 , 34.3058214285  , -124.9536456028, 56.1640195764  ,
+    94.3636873606  , 35.3992852810  , -38.3920852159 , -100.5738062016, -29.7837022314 , 42.9133913996  , -34.2715618187 , -14.3589115627 ,
+    -16.5935468750 , 20.4574192236  , -88.7897972666 , -38.6285080386 , 53.3203422726  , 98.5991486746  , 122.7305462474 , 67.7902817187  ,
+    5.1764117389   , 5.0632821624   , 21.9288789574  , -78.3140512638 , -21.2069682335 , 23.6342010925  , 34.4445769455  , 59.1346766615  ,
+    28.9978778000  , 39.8121180845  , -17.1650033520 , -56.9174900874 , 17.8157086148  , -112.8801457350, -122.4019040408, 140.8669393157 ,
+    -65.4664329639 , 40.6952775518  , 32.7260891658  , -43.2565155866 , 19.3945751928  , -20.1815002000 , -67.6601711640 , -18.1921178207 ,
+    -35.6802153684 , 49.9550290306  , 131.4925251016 , -31.2940938167 , -5.2848453344  , -109.5580577933, 20.2437599390  , -8.8782958734  ,
+    54.1836717264  , 7.2555852190   , -3.5698316137  , -51.9236786262 , 6.7861547980   , -104.4814551670, 45.8458629668  , 70.0890876844  ,
+    38.3572837740  , 61.8024165129  , 68.0176962024  , -12.8193934080 , -21.4661610917 , -0.9377108815  , -74.2100679061 , 71.0490808147  ,
+    91.9813889497  , -14.5797640164 , 3.5036749129   , -138.3605478356, -48.1501349794 , -16.0636922482 , -12.1334197606 , 15.0562207637  ,
+    -34.0878176054 , 55.1075126157  , 97.3829871877  , 0.2053358099   , -94.8713267382 , 51.5460954054  , 21.2966946363  , 58.1331025047  ,
+    -23.4599044132 , -19.3315856528 , -8.4497193577  , -1.9594679356  , -33.1906549336 , -144.6825417978, -57.1218958072 , 35.7353406097  ,
+    61.4666549819  , 14.6536253128  , 82.1632196866  , -44.6230161723 , -91.1022589278 , -18.5737673927 , -136.8975612334, 56.9606788003  ,
+    70.7059960183  , -68.2829345081 , -10.2629800455 , -53.6385325047 , -68.7928766204 , 88.2444688302  , 83.1412324801  , -102.9206928160,
+    -68.2329763159 , -69.7552955469 , 108.2132269009 , -28.2582329307 , 5.6685898328   , -36.0392956840 , 43.3269513128  , -8.6436416796  ,
+    -16.5054886972 , 11.5008791788  , 39.6923606683  , -28.9039554061 , 13.5938214364  , -23.6296332202 , 49.1171161163  , 53.1636857935  ,
+    -62.9672053166 , -54.2594757384 , 48.3838956696  , 8.0469071555   , -33.6472086213 , -120.5381752144, 55.0880453111  , 17.8990740563  ,
+    144.9402232336 , 101.7886229203 , -73.3666393712 , -16.4721379138 , -12.7447935685 , 101.8245160983 , -49.7026860415 , -15.1227790364 ,
+    65.7430288442  , -131.8695390036, 10.2750933946  , 90.9752774838  , -26.5859990591 , -95.6962772568 , 76.2174589344  , 24.8796848060  ,
+    -38.8938223046 , 54.1687774852  , -37.3585968996 , -34.6848570502 , 33.0151011570  , -55.8345877671 , -3.9009101671  , -31.5024971691 ,
+    -9.6863895491  , 91.8719195957  , -58.9993249744 , -25.6887030614 , -8.0829472205  , 4.6386491741   , -71.4019697167 , -21.3734669095 ,
+    86.2079144404  , 79.6823974266  , -0.0910915997  , 44.8067718095  , 58.7204020766  , 72.6856808976  , -50.3373732478 , -116.1175365534,
+    -15.0884909384 , 5.4593772059   , -63.6553527905 , 37.3460388205  , -32.2399421679 , 95.7569350513  , -7.3700141964  , -56.0370832967 ,
+    -41.7377150439 , -42.0042856519 , 12.5134312941  , 93.7845584531  , -32.4801087157 , -33.3976050318 , -24.2252126001 , -46.3199064467 ,
+    -20.3704610276 , 15.8571376404  , 88.9127217235  , -33.1132582267 , -1.0005675836  , -28.1780471904 , 150.9349379135 , 38.0600520828  ,
+    36.4338677563  , -3.3709201641  , 29.7709773016  , 16.5064119077  , 21.3147729463  , 110.6714300904 , 18.8406036507  , 14.8963298097  ,
+    50.9975960392  , 16.3991140350  , -194.0805845907, -41.6723945839 , -74.8991127408 , -6.4587655805  , -0.6883628218  , -49.8709647175 ,
+    194.2265120473 , 64.3043624521  , 16.0040882780  , 68.4032551772  , -43.4050313128 , 84.6826289824  , -28.1357565943 , 134.6895584120 ,
+    -7.9746152680  , -95.6692886462 , -48.9444370342 , 79.4479343188  , -50.5345228122 , 52.4800633307  , -14.7735051703 , -20.1510237050 ,
+    22.5049816980  , 64.4191999102  , 24.8385648232  , 99.4265041360  , 62.0189508473  , -28.3892600378 , -109.8842008564, -79.0407483407 ,
+    18.3408112020  , 49.1650536089  , 31.5419844924  , -36.1160722679 , -132.9148081329, 10.4053531567  , -129.2463715470, -43.4602207151 ,
+    -24.2420653292 , 91.5388317556  , 21.4762248190  , -44.3810909139 , 18.4098011282  , -45.8691164539 , -20.9831197962 , 16.2076792914  ,
+    66.0224147666  , -13.6794615513 , 101.2163279622 , -62.4462618603 , 22.2040981785  , -52.3208382802 , -24.7909079016 , 58.5150375093  ,
+    18.8569705105  , -55.6083430939 , 131.0273367422 , -34.5209015065 , 121.4357296573 , -77.2590299593 , -51.5929566898 , 5.0247131098   ,
+    -23.8451707592 , -4.5912313547  , 31.1387246821  , 61.7019310824  , 49.1912429744  , -50.5836913031 , -74.8182600630 , -21.6209317022 ,
+    20.9409464654  , -72.7870824583 , -28.3530746820 , -45.0794425434 , -13.4910629905 , -62.0158772255 , -34.1421181246 , 44.2844972784  ,
+    8.4213193211   , 79.9349022793  , 60.0160502260  , 32.2272994080  , -72.2893887746 , 17.3063698247  , -134.6335742431, 64.6499736261  ,
+    7.1411921919   , -37.5517577873 , 6.2405670930   , 117.1920927305 , 128.7420689815 , -3.1556854963  , -13.4100422909 , -11.9336372907 ,
+    -8.6022400553  , -102.0033506666, -78.4696575074 , 15.0765861403  , -111.5219718576, -13.4162786508 , 38.2437013694  , 61.1637732561  ,
+    -34.4804160003 , 107.4438003830 , -79.4193067813 , -81.1842853968 , -26.2622970331 , 132.3205425408 , -119.1464268477, 67.3048866598  ,
+    103.3266736715 , -58.1865815617 , 27.6231908601  , -11.2004371750 , 26.0340617206  , 12.5696123916  , 0.6442714420   , -30.7393043544 ,
+    1.5314955897   , 49.9110088250  , -106.1358721920, 51.1608329944  , -32.8684239794 , -27.7215905745 , -11.6450303367 , -36.7731678028 ,
+    59.9383486599  , -4.6301990580  , 5.0361682939   , -10.5669407980 , 124.0908762205 , 35.8305364082  , -123.6216777114, -74.2569079167 ,
+    -56.7651776816 , 16.0736385582  , 23.5030632215  , -110.6764295938, 44.3086821806  , 9.4452708243   , 5.3300080251   , 39.0483916714  ,
+    151.4550562868 , 62.8957092621  , -116.8103461233, 5.1129927759   , -33.2252515135 , -9.4522506046  , 22.7026048372  , -15.5264414569 ,
+    71.2087620034  , 19.1191568332  , 50.3019546809  , -5.6096922409  , 22.9344126462  , -7.7591876203  , 31.8949515564  , -58.4253952381 ,
+    66.4341297173  , -19.0583083044 , 96.7695087855  , 20.4934280047  , 4.9544603116   , -20.8288135920 , -173.2659655408, -62.4883621640 ,
+    -48.5528422703 , 12.1437504278  , 60.2482234666  , -19.6072312919 , -34.6320214291 , 129.0089698963 , -50.9042160618 , 98.3952661477  ,
+    -4.7051792479  , -13.1768910826 , 69.5138802139  , 58.5748201565  , -45.9385652563 , 151.7952104306 , 34.2541941013  , -58.0417838381 ,
+    28.1480473670  , 46.4006562684  , 97.7001828545  , 4.0855607626   , -32.6097018162 , 16.8913949959  , 105.7266202978 , -89.3978374651 ,
+    -60.9338593128 , -41.2220734230 , 49.9393070783  , 95.0974764854  , 49.2498366456  , 58.6214364590  , 34.1113830569  , 45.6634098874  ,
+    -22.5356086770 , -97.1978653617 , 86.5565049535  , 70.6118545777  , -30.6978082909 , 118.7238621666 , 14.5922386932  , 11.3449652072  ,
+    65.6007783405  , 82.6369678204  , -52.0390492248 , -47.0160551227 , -95.5142448634 , 99.7162626888  , -36.5523815090 , -42.8042935534 ,
+    68.3566199798  , -13.8451547552 , -71.1629911780 , 36.2989433752  , -32.4867163365 , 112.4079947071 , -75.6295117422 , 47.5276421639  ,
+    51.8078250755  , -26.8715188457 , -9.6291144797  , 40.1999849640  , -38.4634033246 , 40.9764960915  , -26.1715730268 , 36.5996396515  ,
+    -26.9924731886 , 53.7879986570  , -83.1658398348 , 23.6381378489  , 43.8794937753  , -55.4133836419 , 90.0266130838  , 14.1036181982  ,
+    -18.1225736715 , 85.1363181151  , -62.5970846379 , -18.5291947838 , -25.7341986703 , -49.7061342931 , -59.0442763971 , 50.8960636803  ,
+    -87.6471123430 , -36.7217762531 , 22.5952364054  , 11.1107885650  , -0.5377327229  , 160.8145792630 , 73.3103441505  , 10.1656872354  ,
+    -50.4554350397 , -57.3478171016 , -15.4201715357 , -26.9135446491 , -4.9891264771  , -37.0226770057 , -80.9919535641 , 50.4418660876  ,
+    -25.8517575250 , -69.9538258421 , -17.5730160671 , 15.9405836751  , 113.9545230349 , -46.1040379057 , -94.2458635014 , -69.0338522452 ,
+    43.5813790265  , 107.1836101171 , -55.1012654323 , -77.1529555887 , -33.1530320656 , -94.5582659641 , -53.6837586872 , 27.0680381378  ,
+    93.9385415207  , -61.0955216188 , 18.0530957225  , 7.9150142320   , -12.1218191587 , 34.0173961457  , 40.0084937565  , 9.8119275580   ,
+    44.2065861274  , -1.8718514394  , 67.4740024215  , 46.7391150131  , 207.2404815875 , 45.1635364462  , 43.3580102761  , -44.0244218674 ,
+    83.2387206007  , -8.6441851856  , 12.3993902588  , -22.5091685270 , -19.8332981376 , 97.9196509289  , -76.6720306234 , 28.9740705859  ,
+    121.9415248016 , 9.6656982611   , -51.0996453694 , 37.3704374740  , 74.7589840907  , -113.4066752631, 120.0029566342 , -105.3786221360,
+    81.8152755619  , -13.4979932982 , -21.4680758393 , -85.1088235539 , -65.3610798409 , -35.0444139470 , -48.0220794487 , -41.6210317362 ,
+    33.1212995259  , -82.1480936443 , -10.5479715135 , 76.4601917004  , 42.1983651157  , 92.6104239912  , -42.3536237955 , -24.5644182272 ,
+    30.4446637772  , -90.2899420489 , 63.6723540422  , 103.0895811428 , 64.1706769263  , -10.7069812309 , 21.8927240409  , 6.3571071738   ,
+    57.1457649358  , -52.9866276448 , 66.0981829072  , -29.5372056881 , -79.2252039810 , -136.2440652798, -57.0106422562 , 86.8203548141  ,
+    66.4244149837  , 53.3230426111  , -66.1283059222 , -131.0402660353, 8.0548411081   , 122.9088988100 , 1.2626894208   , -60.5059112373 ,
+    -68.8707203082 , -6.4747987200  , 85.8411327244  , 99.9624156733  , 90.4197864338  , -35.9630441182 , -22.9158275507 , -17.3660128776 ,
+    16.7845345761  , 34.7219749782  , -39.3513765878 , 1.0460702756   , -60.9494500182 , 20.0900333387  , -85.9636743832 , 88.4400782168  ,
+    15.0729628728  , 61.5499846243  , 11.8579871757  , 107.8617581581 , -42.9393027864 , -62.8422307621 , -19.0589600542 , 4.0750325807   ,
+    -36.0651825425 , 55.7638724501  , -10.4691736080 , -55.5672537178 , -61.2061519915 , -21.1885348576 , -131.2535612498, 24.7463552676  ,
+    22.9426321237  , 14.3038202264  , -138.0926317438, -59.0892900856 , -162.5416439986, 7.1307658250   , -141.1236672256, -4.7173618068  ,
+    -16.7741532807 , -68.2615451173 , -2.6608701102  , 84.1978109826  , -11.3446202072 , 59.9630033088  , -1.8994925010  , -37.9301641959 ,
+    -119.4435600954, -11.4587491646 , 12.2423215240  , -7.3169898616  , -67.0373621128 , 36.0198843055  , 53.9791315249  , -134.5885680695,
+    -83.8330811965 , -16.6714816463 , -8.8498552035  , -24.0513088196 , -22.9444328877 , -37.7961441531 , 25.1975736186  , -136.1611637464,
+    -5.0843464033  , -10.3939554694 , 20.7422826935  , 75.6854136623  , 46.4179626736  , -57.0052830175 , 7.3457235521   , -51.5504447254 ,
+    -158.4375751701, -200.2426967181, -48.1234996261 , 1.6623945527   , 21.1746524375  , 99.4092980367  , -2.3206772903  , 45.7989166757  ,
+    2.0181548348   , -88.0556010969 , -59.1527212096 , 47.3607925077  , -10.4181140309 , 56.3558125650  , -8.9799125560  , -30.0376711812 ,
+    -36.7132904688 , 35.7785050392  , -13.0763909369 , -2.1855594714  , 18.1550954005  , -28.6711803575 , -55.4495172398 , -2.8812973198  ,
+    -59.9575059158 , 40.0588875786  , 57.4713686602  , -3.2835144853  , -36.7193552111 , -64.9415131516 , -166.9555466445, -23.5556853844 ,
+    -54.9408569587 , -35.2310451959 , 21.3345143458  , 65.7590671151  , 51.2214538168  , 46.1271939944  , -42.2235267919 , 127.2329928299 ,
+    105.2391778600 , 17.6726845966  , -129.9021148044, 8.7065613044   , -94.0987112511 , -3.5375742950  , -23.1385452379 , 60.6219530633  ,
+    92.5445564235  , 48.5111974469  , -52.5699309159 , -60.0634811685 , 25.9034368684  , 140.0249495491 , 1.5918852392   , 38.0266038291  ,
+    17.5588710703  , 3.4294066089   , -27.6748782173 , 59.6182974489  , -35.2924781853 , -38.6198576115 , -13.6119803198 , 7.8375587489   ,
+    22.7250686519  , -28.3524510951 , -34.4269062817 , 22.6464817325  , -61.6528147860 , -5.9782002429  , 61.4730771294  , 43.5582379527  ,
+    55.6862408270  , 87.8745651631  , 46.3401042715  , -19.8780979663 , 74.1272633369  , 29.8590452377  , -12.8665765140 , 34.2931401219  ,
+    53.9279617551  , -16.9017895140 , -70.1527553166 , -79.6367897992 , 109.3728271017 , -129.2214826835, -53.4644539730 , -51.5654458993 ,
+    17.6062148433  , 3.5090251835   , 74.2615941204  , -109.3431097845, 40.1403465151  , 28.8714561280  , 94.0868659302  , -19.0047033845 ,
+    -60.0967410050 , -19.0998457619 , -67.2027075128 , 72.0711434846  , -17.8737851232 , 123.7050551274 , 132.6331504104 , 25.5018761009  ,
+    -36.7817189239 , -29.1580893235 , -6.5848563828  , 90.2868948516  , -35.7017258498 , -68.5675432955 , -52.4888589786 , 47.1377730021  ,
+    -7.4546621940  , -52.0657517138 , -49.0404829633 , -114.6910280126, -117.6819819437, -32.7856729408 , 31.8232065591  , 12.1192973039  ,
+    35.2678513420  , -1.0336778293  , 30.7021249679  , 127.0442906046 , -84.8457819393 , 28.9862843096  , -47.3524701726 , -126.1094998460,
+    -2.9700276582  , -2.4956545870  , -53.8624121141 , -85.2114117637 , 76.9057985618  , 137.1205201755 , -19.0830817212 , 14.3407526579  ,
+    -56.5921994449 , -25.6084873186 , -44.9470801106 , -133.3139496090, 0.3487447576   , 33.4499716730  , 34.7126257844  , -9.3307383323  ,
+    27.2996276947  , 10.8765676134  , -91.1032360444 , -90.9584216222 , 1.6981490570   , 96.8557438791  , 56.7726390913  , -44.3246449237 ,
+    52.3260643361  , 21.5551140465  , 27.4535327381  , 2.0072717479   , 7.4823125629   , 77.1185863870  , 16.1372262663  , -10.7206012957 ,
+    66.8830091413  , 49.3523828287  , 54.0855375598  , 30.8570349345  , -10.9255375390 , 62.3910624674  , 30.9238561381  , 0.3352881853   ,
+    72.1022806197  , -28.8319885008 , 23.3335288806  , 46.8999035980  , -67.0984424822 , -164.7917209112, 42.5767681360  , -92.4668227688 ,
+    43.8491734282  , -17.1126540408 , 37.4819594334  , 69.0774409673  , -39.3530526854 , -14.0693747124 , -60.2520781215 , -80.3860105519 ,
+    32.6689956840  , 15.3393042576  , -18.5529761307 , 97.3942151573  , -4.4462855745  , 13.7614349817  , 158.3358780719 , -44.7258299667 ,
+    -17.7741912819 , 116.5136962268 , -33.6261057820 , 22.8344441288  , -155.1423976144, 5.7070117893   , -22.7906543902 , -45.0633909283 ,
+    -13.9329987929 , -66.0848932507 , 1.1383038109   , 123.8386958483 , 67.6662401589  , 45.9152963554  , -27.4397697462 , 97.9596747354  ,
+    -6.3544655181  , 29.0832146722  , 96.3468162499  , 32.4535976137  , -91.0650399301 , 2.7293262791   , 70.7853483111  , -92.3655274571 ,
+    69.0359217256  , 83.1530567979  , 35.8375091111  , 7.3393552348   , -95.1770165365 , 76.4905790891  , 55.6253140577  , -29.5315327050 ,
+    -16.5935468750 , 20.4574192236  , -88.7897972666 , -38.6285080386 , 53.3203422726  , 98.5991486746  , 122.7305462474 , 67.7902817187  ,
+    5.1764117389   , 5.0632821624   , 21.9288789574  , -78.3140512638 , -21.2069682335 , 23.6342010925  , 34.4445769455  , 59.1346766615  ,
+    28.9978778000  , 39.8121180845  , -17.1650033520 , -56.9174900874 , 17.8157086148  , -112.8801457350, -122.4019040408, 140.8669393157 ,
+    -65.4664329639 , 40.6952775518  , 32.7260891658  , -43.2565155866 , 19.3945751928  , -20.1815002000 , -67.6601711640 , -18.1921178207 ,
+    -35.6802153684 , -19.6571455162
+};
+
+/*--------------------------------------------------------------------------------*/
+/* Blocksizes */
+/*--------------------------------------------------------------------------------*/
+ARR_DESC_DEFINE(uint32_t,
+                filtering_blocksizes,
+                5,
+                CURLY(
+                      1, 7, 14, 32, FILTERING_MAX_BLOCKSIZE));
+
+ARR_DESC_DEFINE(uint32_t,
+                lms_blocksizes,
+                3,
+                CURLY(
+                      128, 256, LMS_MAX_BLOCKSIZE));
+
+ARR_DESC_DEFINE(uint16_t,
+                filtering_numtaps,
+                5,
+                CURLY(
+                      4, 6, 14, 32, FILTERING_MAX_NUMTAPS));
+
+ARR_DESC_DEFINE(uint16_t,
+                filtering_numtaps2,
+                5,
+                CURLY(
+                      6, 12, 18, 24, 30));
+
+ARR_DESC_DEFINE(uint16_t,
+                filtering_numstages,
+                3,
+                CURLY(
+                      1, 7, FILTERING_MAX_NUMSTAGES));
+
+ARR_DESC_DEFINE(uint8_t,
+                filtering_postshifts,
+                3,
+                CURLY(
+                      0, 1, FILTERING_MAX_POSTSHIFT));
+
+ARR_DESC_DEFINE(uint8_t,
+                filtering_Ls,
+                3,
+                CURLY(
+                      1, 2, FILTERING_MAX_L));
+
+ARR_DESC_DEFINE(uint8_t,
+                filtering_Ms,
+                6,
+                CURLY(
+                      1, 2, 4, 7, 11, FILTERING_MAX_M));
+
+
+/*--------------------------------------------------------------------------------*/
+/* Coefficient Lists */
+/*--------------------------------------------------------------------------------*/
+
+// There must be at least max( FILTERING_MAX_NUMTAPS + 2 , FILTERING_MAX_NUMSTAGES * 6 + 2) coefficients
+const float32_t filtering_coeffs_f32[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+	-13.0572f, 0.0f     , -97.4724f, 8.4111f  , -7.2193f , -53.7577f, 22.2630f ,
+   -1.0509f  , -25.9198f, 26.5207f , -12.6697f, -78.7453f, -0.6540f , 0.3119f  ,
+   13.4595f  , -6.7225f , -4.1313f , -38.5974f, 3.2700f  , -51.6191f, -22.4314f,
+   0.2481f   , 32.9779f , -37.6421f, 5.4469f  , -7.0023f , 24.3657f , 9.9140f  ,
+   0.2870f   , -13.0499f, 29.3333f , -53.1396f, -2.7555f , 0.5377f  , 35.3491f ,
+   -3.7134f  , 0.8548f  , 4.7469f  , -10.5865f, -2.7285f , -1.5912f , -13.3502f,
+   6.8532f   , -8.2304f , -8.1193f , 3.8257f  , -2.1703f , 13.5727f , 14.2736f ,
+   -0.9855f  , -8.9334f , -13.8883f, 11.8430f , -2.2024f , 0.9795f  , 15.6191f ,
+   5.2121f   , 10.8102f , -9.4171f , 6.0411f  , -0.9131f , 10.6992f , -3.2634f ,
+   7.5849f   , -4.9305f , -6.0549f , -7.9409f , 1.5827f  , 13.3177f , 8.6727f  ,
+   -13.2268f , 11.1239f , 0.2481f  , 32.9779f , -37.6421f, 5.4469f  , -13.8883f,
+   11.8430f  , -2.2024f , 0.9795f  , 15.6191f , 0.2481f  , 32.9779f , -37.6421f,
+   3.2700f   , -51.6191f
+};
+const float64_t filtering_coeffs_f64[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+	-13.0572f, 0.0f     , -97.4724f, 8.4111f  , -7.2193f , -53.7577f, 22.2630f ,
+   -1.0509f  , -25.9198f, 26.5207f , -12.6697f, -78.7453f, -0.6540f , 0.3119f  ,
+   13.4595f  , -6.7225f , -4.1313f , -38.5974f, 3.2700f  , -51.6191f, -22.4314f,
+   0.2481f   , 32.9779f , -37.6421f, 5.4469f  , -7.0023f , 24.3657f , 9.9140f  ,
+   0.2870f   , -13.0499f, 29.3333f , -53.1396f, -2.7555f , 0.5377f  , 35.3491f ,
+   -3.7134f  , 0.8548f  , 4.7469f  , -10.5865f, -2.7285f , -1.5912f , -13.3502f,
+   6.8532f   , -8.2304f , -8.1193f , 3.8257f  , -2.1703f , 13.5727f , 14.2736f ,
+   -0.9855f  , -8.9334f , -13.8883f, 11.8430f , -2.2024f , 0.9795f  , 15.6191f ,
+   5.2121f   , 10.8102f , -9.4171f , 6.0411f  , -0.9131f , 10.6992f , -3.2634f ,
+   7.5849f   , -4.9305f , -6.0549f , -7.9409f , 1.5827f  , 13.3177f , 8.6727f  ,
+   -13.2268f , 11.1239f , 0.2481f  , 32.9779f , -37.6421f, 5.4469f  , -13.8883f,
+   11.8430f  , -2.2024f , 0.9795f  , 15.6191f , 0.2481f  , 32.9779f , -37.6421f,
+   3.2700f   , -51.6191f
+};
+
+const float32_t filtering_coeffs_b_f32[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+	-0.0572f, 0.0f    , -0.4724f, 0.4111f , -0.9999f, -0.7577f, 0.2630f ,
+   -0.0509f, -1.0000f, 0.5207f , -0.6697f, -0.7453f, -0.6540f, 0.3119f ,
+   0.4595f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, -0.4314f,
+   0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f ,
+   0.2870f , -0.0499f, 0.3333f , -0.1396f, -0.7555f, 0.5377f , 0.3491f ,
+   0.2369f , -0.5310f, -0.5904f, 0.6263f , 0.0205f , 0.1088f , -0.2926f,
+   -0.4187f, -0.5094f, 0.4479f , -0.3594f, -0.3102f, 0.6748f , 0.7620f ,
+   0.0033f , -0.9195f, 0.3192f , -0.1705f, 0.5524f , -0.5025f, 0.4898f ,
+   -0.0119f, -0.3982f, -0.7818f, -0.9186f, -0.0944f, 0.7228f , 0.7014f ,
+   0.4850f , -0.6814f, 0.4914f , -0.6286f, 0.5130f , -0.8585f, 0.3000f ,
+   0.6068f , 0.4978f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f,
+   0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f ,
+   0.2369f , -0.5310f
+};
+
+const float64_t filtering_coeffs_b_f64[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+	-0.0572f, 0.0f    , -0.4724f, 0.4111f , -0.9999f, -0.7577f, 0.2630f ,
+   -0.0509f, -1.0000f, 0.5207f , -0.6697f, -0.7453f, -0.6540f, 0.3119f ,
+   0.4595f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f, -0.4314f,
+   0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f ,
+   0.2870f , -0.0499f, 0.3333f , -0.1396f, -0.7555f, 0.5377f , 0.3491f ,
+   0.2369f , -0.5310f, -0.5904f, 0.6263f , 0.0205f , 0.1088f , -0.2926f,
+   -0.4187f, -0.5094f, 0.4479f , -0.3594f, -0.3102f, 0.6748f , 0.7620f ,
+   0.0033f , -0.9195f, 0.3192f , -0.1705f, 0.5524f , -0.5025f, 0.4898f ,
+   -0.0119f, -0.3982f, -0.7818f, -0.9186f, -0.0944f, 0.7228f , 0.7014f ,
+   0.4850f , -0.6814f, 0.4914f , -0.6286f, 0.5130f , -0.8585f, 0.3000f ,
+   0.6068f , 0.4978f , -0.7225f, -0.1313f, -0.5974f, 0.2700f , -0.6191f,
+   0.2481f , 0.9779f , -0.6421f, 0.4469f , -0.0023f, 0.3657f , 0.9140f ,
+   0.2369f , -0.5310f
+};
+
+const float32_t *filtering_coeffs_c_f32 = filtering_coeffs_b_f32 + 1;
+
+const q31_t filtering_coeffs_q31[FILTERING_MAX_NUMSTAGES * 6 + 2] =
+{
+	0xEEDA759C, 0x00000000, 0x80000000, 0x0B0BA027, 0xF6850544, 0xB967E3EC,
+	0x1D3C4F64, 0xFFFFFFFF, 0xDDF65B14, 0x22D3A62D, 0xEF5CBB89, 0x98979EE0,
+	0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5,
+	0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690,
+	0x0727234D, 0xF6CDFB14, 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A,
+	0x268530EF, 0xBA37B050, 0x7FFFFFFF, 0xEF5CBB89, 0x00000000, 0x2B4E6639,
+	0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5,
+	0x1D3C4F64, 0xFFFFFFFF, 0xDDF65B14, 0x22D3A62D, 0xEF5CBB89, 0x98979EE0,
+	0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690,
+	0x0727234D, 0xF6CDFB14, 0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A,
+   0xE28B1589, 0x0053690B, 0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0xB967E3EC,
+	0x044B50CD, 0xBC36D4BC, 0xE28B1589, 0x0053690B, 0x2B4E6639, 0xCE919690,
+   0x1FFF2FCF, 0x0D04DC35, 0x00607E4D, 0xEEDCF04A, 0xFFFFFFFF, 0xDDF65B14,
+	0xFF242597, 0x0068D9E9, 0x11ACC4F3, 0xF72C0F21, 0xFA9326BC, 0xCD506BD5,
+   0x2B4E6639, 0xCE919690
+};
+
+const q31_t *filtering_coeffs_b_q31 = filtering_coeffs_q31 + 1;
+const q31_t *filtering_coeffs_c_q31 = filtering_coeffs_q31 + 2;
+
+//fourth coefficient MUST be zero for arm_biquad_cascade_df1_fast_q15 to work
+//every 6th coefficient after that must also be zero
+const q15_t filtering_coeffs_q15[FILTERING_MAX_NUMSTAGES * 6 + 4] =
+{
+	0xBA37, 0xEEDA, 0x8000, 0x0000, 0x0B0B, 0xF685, 0xB967,
+	0x1D3C, 0xFFFF, 0x0000, 0x22D3, 0xEF5C, 0x9897,
+	0xFF24, 0x0068, 0x0000, 0xF72C, 0xFA93, 0xCD50,
+	0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91,
+	0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC,
+	0x2685, 0xBA37, 0x0000, 0xDDF6, 0x0000, 0x2B4E,
+	0xFF24, 0x0068, 0x0000, 0xF72C, 0xFA93, 0xCD50,
+	0x1D3C, 0xFFFF, 0x0000, 0x22D3, 0xEF5C, 0x9897,
+	0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91,
+	0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC,
+   0xE28B, 0x0053, 0x0000, 0xBC36, 0xE28B, 0xB967,
+	0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91,
+	0x044B, 0xBC36, 0x0000, 0x0053, 0x2B4E, 0xCE91,
+	0x0727, 0xF6CD, 0x0000, 0x0D04, 0x0060, 0xEEDC,
+   0xE28B, 0x11AC, 0x0000,
+};
+
+const q15_t *filtering_coeffs_b_q15 = filtering_coeffs_q15 + 2;
+const q15_t *filtering_coeffs_c_q15 = filtering_coeffs_q15 + 4;
+
+const q7_t filtering_coeffs_q7[FILTERING_MAX_NUMSTAGES * 6 + 8] =
+{
+	0xEE, 0x00, 0x80, 0x0B, 0xF6, 0xB9,
+	0x1D, 0xFF, 0xDD, 0x22, 0xEF, 0x98,
+	0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xCD,
+	0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE,
+	0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+	0x26, 0xBA, 0x7F, 0x00, 0x80, 0x2B,
+	0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xCD,
+	0x1D, 0xFF, 0xDD, 0x22, 0xEF, 0x98,
+	0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE,
+	0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+   0xE2, 0x00, 0x04, 0xBC, 0xE2, 0xB9,
+	0x04, 0xBC, 0xE2, 0x00, 0x2B, 0xCE,
+	0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+	0x26, 0xBA, 0x7F, 0x00, 0x80, 0x2B,
+	0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+   0xFA, 0xCD
+};
+
+const q7_t *filtering_coeffs_b_q7 = filtering_coeffs_q7 + 4;
+const q7_t *filtering_coeffs_c_q7 = filtering_coeffs_q7 + 8;
+
+/*--------------------------------------------------------------------------------*/
+/* Tap Delay Lists */
+/*--------------------------------------------------------------------------------*/
+//const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS] = {
+//	0xEE, 0x00, 0x10, 0x0B, 0xF6, 0xD9,
+//	0x1D, 0xFF, 0xDD, 0x1A, 0xEF, 0xE8,
+//	0xFF, 0x00, 0x11, 0xF7, 0xFA, 0xDD,
+//	0x04, 0xEC, 0xE2, 0x00, 0x2B, 0xFE,
+//	0x07, 0xF6, 0x1F, 0x0D, 0x00, 0xEE,
+//	0x20, 0xDF, 0x21
+//};
+
+const int32_t filtering_tap_delay[FILTERING_MAX_NUMTAPS] = {
+	0x00, 0x01, 0x10, 0x0B, 0x03, 0x05,
+	0x1D, 0x21, 0x11, 0x1A, 0x1F, 0x07,
+	0x20, 0x01, 0x10, 0x0B, 0x03, 0x05,
+	0x1D, 0x21, 0x11, 0x1A, 0x1F, 0x07,
+	0x00, 0x01, 0x10, 0x0B, 0x03, 0x05,
+	0x1D, 0x21, 0x11
+};
+

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c

+#include "jtest.h"
+#include "filtering_tests.h"
+
+JTEST_DEFINE_GROUP(filtering_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_GROUP_CALL(biquad_tests);
+    JTEST_GROUP_CALL(conv_tests);
+    JTEST_GROUP_CALL(correlate_tests);
+    JTEST_GROUP_CALL(fir_tests);
+    JTEST_GROUP_CALL(iir_tests);
+    JTEST_GROUP_CALL(lms_tests);
+
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c

+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+#define FIR_DEFINE_TEST(suffix, config_suffix, output_type)             \
+   JTEST_DEFINE_TEST(arm_fir##config_suffix##_##suffix##_test,          \
+         arm_fir##config_suffix##_##suffix)                             \
+   {                                                                    \
+      arm_fir_instance_##suffix fir_inst_fut = { 0 };                   \
+      arm_fir_instance_##suffix fir_inst_ref = { 0 };                   \
+                                                                        \
+      TEMPLATE_DO_ARR_DESC(                                             \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes    \
+            ,                                                           \
+         TEMPLATE_DO_ARR_DESC(                                          \
+               numtaps_idx, uint16_t, numTaps, filtering_numtaps        \
+               ,                                                        \
+               /* Initialize the FIR Instances */                       \
+               arm_fir_init_##suffix(                                   \
+                     &fir_inst_fut, numTaps,                            \
+                     (output_type*)filtering_coeffs_##suffix,           \
+                     (void *) filtering_pState, blockSize);             \
+                                                                        \
+              /* Display test parameter values */                       \
+              JTEST_DUMP_STRF("Block Size: %d\n"                        \
+                              "Number of Taps: %d\n",                   \
+                         (int)blockSize,                                \
+                         (int)numTaps);                                 \
+                                                                        \
+               JTEST_COUNT_CYCLES(                                      \
+                     arm_fir##config_suffix##_##suffix(                 \
+                           &fir_inst_fut,                               \
+                           (void *) filtering_##suffix##_inputs,        \
+                           (void *) filtering_output_fut,               \
+                           blockSize));                                 \
+                                                                        \
+               arm_fir_init_##suffix(                                   \
+                     &fir_inst_ref, numTaps,                            \
+                     (output_type*)filtering_coeffs_##suffix,           \
+                     (void *) filtering_pState, blockSize);             \
+                                                                        \
+               ref_fir##config_suffix##_##suffix(                       \
+                     &fir_inst_ref,                                     \
+                     (void *) filtering_##suffix##_inputs,              \
+                     (void *) filtering_output_ref,                     \
+                     blockSize);                                        \
+                                                                        \
+               FILTERING_SNR_COMPARE_INTERFACE(                         \
+                     blockSize,                                         \
+                     output_type)));                                    \
+                                                                        \
+            return JTEST_TEST_PASSED;                                   \
+   }
+
+#define FIR_INTERPOLATE_DEFINE_TEST(suffix, output_type)                      \
+   JTEST_DEFINE_TEST(arm_fir_interpolate_##suffix##_test,                     \
+         arm_fir_interpolate_##suffix)                                        \
+   {                                                                          \
+      arm_fir_interpolate_instance_##suffix fir_inst_fut = { 0 };             \
+      arm_fir_interpolate_instance_##suffix fir_inst_ref = { 0 };             \
+                                                                              \
+      TEMPLATE_DO_ARR_DESC(                                                   \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes          \
+            ,                                                                 \
+         TEMPLATE_DO_ARR_DESC(                                                \
+               numtaps_idx, uint16_t, numTaps, filtering_numtaps2             \
+               ,                                                              \
+            TEMPLATE_DO_ARR_DESC(                                             \
+                  L_idx, uint8_t, L, filtering_Ls                             \
+                  ,                                                           \
+                  /* Display test parameter values */                         \
+                  JTEST_DUMP_STRF("Block Size: %d\n"                          \
+                                 "Number of Taps: %d\n"                       \
+                                 "Upsample factor: %d\n",                     \
+                                (int)blockSize,                               \
+                                (int)numTaps,                                 \
+                                (int)L);                                      \
+                                                                              \
+                  /* Initialize the FIR Instances */                          \
+                  arm_fir_interpolate_init_##suffix(                          \
+                        &fir_inst_fut, L, numTaps,                            \
+                        (output_type*)filtering_coeffs_##suffix,              \
+                        (void *) filtering_pState, blockSize);                \
+                                                                              \
+                  JTEST_COUNT_CYCLES(                                         \
+                        arm_fir_interpolate_##suffix(                         \
+                              &fir_inst_fut,                                  \
+                              (void *) filtering_##suffix##_inputs,           \
+                              (void *) filtering_output_fut,                  \
+                              blockSize));                                    \
+                                                                              \
+                  arm_fir_interpolate_init_##suffix(                          \
+                        &fir_inst_ref, L, numTaps,                            \
+                        (output_type*)filtering_coeffs_##suffix,              \
+                        (void *) filtering_pState, blockSize);                \
+                                                                              \
+                  ref_fir_interpolate_##suffix(                               \
+                        &fir_inst_ref,                                        \
+                        (void *) filtering_##suffix##_inputs,                 \
+                        (void *) filtering_output_ref,                        \
+                        blockSize);                                           \
+                                                                              \
+                  FILTERING_SNR_COMPARE_INTERFACE(                            \
+                        blockSize * (uint32_t)L,                              \
+                        output_type))));                                      \
+                                                                              \
+            return JTEST_TEST_PASSED;                                         \
+   }
+
+#define FIR_DECIMATE_DEFINE_TEST(suffix, config_suffix, output_type)       \
+   JTEST_DEFINE_TEST(arm_fir_decimate##config_suffix##_##suffix##_test,    \
+         arm_fir_decimate##config_suffix##_##suffix)                       \
+   {                                                                       \
+      arm_fir_decimate_instance_##suffix fir_inst_fut = { 0 };             \
+      arm_fir_decimate_instance_##suffix fir_inst_ref = { 0 };             \
+                                                                           \
+      TEMPLATE_DO_ARR_DESC(                                                \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes       \
+            ,                                                              \
+         TEMPLATE_DO_ARR_DESC(                                             \
+               numtaps_idx, uint16_t, numTaps, filtering_numtaps           \
+               ,                                                           \
+            TEMPLATE_DO_ARR_DESC(                                          \
+                  M_idx, uint8_t, M, filtering_Ms                          \
+                  ,                                                        \
+                  if (blockSize % M == 0)                                   \
+                  {                                                        \
+                     /* Display test parameter values */                   \
+                     JTEST_DUMP_STRF("Block Size: %d\n"                    \
+                                     "Number of Taps: %d\n"                \
+                                     "Decimation Factor: %d\n",            \
+                                     (int)blockSize,                       \
+                                     (int)numTaps,                         \
+                                     (int)M);                              \
+                                                                           \
+                     /* Initialize the FIR Instances */                    \
+                     arm_fir_decimate_init_##suffix(                       \
+                           &fir_inst_fut, numTaps, M,                      \
+                           (output_type*)filtering_coeffs_##suffix,        \
+                           (void *) filtering_pState, blockSize);          \
+                                                                           \
+                     JTEST_COUNT_CYCLES(                                   \
+                           arm_fir_decimate##config_suffix##_##suffix(     \
+                                 &fir_inst_fut,                            \
+                                 (void *) filtering_##suffix##_inputs,     \
+                                 (void *) filtering_output_fut,            \
+                                 blockSize));                              \
+                                                                           \
+                     arm_fir_decimate_init_##suffix(                       \
+                           &fir_inst_ref, numTaps, M,                      \
+                           (output_type*)filtering_coeffs_##suffix,        \
+                           (void *) filtering_pState, blockSize);          \
+                                                                           \
+                     ref_fir_decimate##config_suffix##_##suffix(           \
+                           &fir_inst_ref,                                  \
+                           (void *) filtering_##suffix##_inputs,           \
+                           (void *) filtering_output_ref,                  \
+                           blockSize);                                     \
+                                                                           \
+                     FILTERING_SNR_COMPARE_INTERFACE(                      \
+                           blockSize / M,                                  \
+                           output_type);                                   \
+                  })));                                                    \
+                                                                           \
+            return JTEST_TEST_PASSED;                                      \
+   }
+
+#define FIR_LATTICE_DEFINE_TEST(suffix, output_type)                       \
+   JTEST_DEFINE_TEST(arm_fir_lattice_##suffix##_test,                      \
+         arm_fir_lattice_##suffix)                                         \
+   {                                                                       \
+      arm_fir_lattice_instance_##suffix fir_inst_fut = { 0 };              \
+      arm_fir_lattice_instance_##suffix fir_inst_ref = { 0 };              \
+                                                                           \
+      TEMPLATE_DO_ARR_DESC(                                                \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes       \
+            ,                                                              \
+         TEMPLATE_DO_ARR_DESC(                                             \
+               numstages_idx, uint16_t, numStages, filtering_numstages     \
+               ,                                                           \
+               /* Display test parameter values */                         \
+               JTEST_DUMP_STRF("Block Size: %d\n"                          \
+                               "Number of Stages: %d\n",                   \
+                               (int)blockSize,                             \
+                               (int)numStages);                            \
+                                                                           \
+               /* Initialize the FIR Instances */                          \
+               arm_fir_lattice_init_##suffix(                              \
+                     &fir_inst_fut, numStages,                             \
+                     (output_type*)filtering_coeffs_##suffix,              \
+                     (void *) filtering_pState);                           \
+                                                                           \
+               JTEST_COUNT_CYCLES(                                         \
+                     arm_fir_lattice_##suffix(                             \
+                           &fir_inst_fut,                                  \
+                           (void *) filtering_##suffix##_inputs,           \
+                           (void *) filtering_output_fut,                  \
+                           blockSize));                                    \
+                                                                           \
+               arm_fir_lattice_init_##suffix(                              \
+                     &fir_inst_ref, numStages,                             \
+                     (output_type*)filtering_coeffs_##suffix,              \
+                     (void *) filtering_pState);                           \
+                                                                           \
+               ref_fir_lattice_##suffix(                                   \
+                     &fir_inst_ref,                                        \
+                     (void *) filtering_##suffix##_inputs,                 \
+                     (void *) filtering_output_ref,                        \
+                     blockSize);                                           \
+                                                                           \
+               FILTERING_SNR_COMPARE_INTERFACE(                            \
+                     blockSize,                                            \
+                     output_type)));                                       \
+                                                                           \
+            return JTEST_TEST_PASSED;                                      \
+   }
+
+
+#define FIR_SPARSE_DEFINE_TEST(suffix, output_type)                     \
+   JTEST_DEFINE_TEST(arm_fir_sparse_##suffix##_test,                    \
+         arm_fir_sparse_##suffix)                                       \
+   {                                                                    \
+      arm_fir_sparse_instance_##suffix fir_inst_fut = { 0 };            \
+      arm_fir_sparse_instance_##suffix fir_inst_ref = { 0 };            \
+                                                                        \
+      TEMPLATE_DO_ARR_DESC(                                             \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes    \
+            ,                                                           \
+         TEMPLATE_DO_ARR_DESC(                                          \
+               numtaps_idx, uint16_t, numTaps, filtering_numtaps        \
+               ,                                                        \
+               /* Display test parameter values */                      \
+               JTEST_DUMP_STRF("Block Size: %d\n"                       \
+                               "Number of Taps: %d\n"                   \
+                               "Tap Delay: %d\n",                       \
+                               (int)blockSize,                          \
+                               (int)numTaps,                            \
+                               (int)FILTERING_MAX_TAP_DELAY);           \
+                                                                        \
+               /* Initialize the FIR Instances */                       \
+               arm_fir_sparse_init_##suffix(                            \
+                     &fir_inst_fut, numTaps,                            \
+                     (output_type*)filtering_coeffs_##suffix,           \
+                     (void *) filtering_pState,                         \
+                     (int32_t*)filtering_tap_delay,                     \
+                     FILTERING_MAX_TAP_DELAY, blockSize);               \
+                                                                        \
+               JTEST_COUNT_CYCLES(                                      \
+                     arm_fir_sparse_##suffix(                           \
+                           &fir_inst_fut,                               \
+                           (void *) filtering_##suffix##_inputs,        \
+                           (void *) filtering_output_fut,               \
+                           (void *) filtering_scratch,                  \
+                           blockSize));                                 \
+                                                                        \
+               arm_fir_sparse_init_##suffix(                            \
+                     &fir_inst_ref, numTaps,                            \
+                     (output_type*)filtering_coeffs_##suffix,           \
+                     (void *) filtering_pState,                         \
+                     (int32_t*)filtering_tap_delay,                     \
+                     FILTERING_MAX_TAP_DELAY, blockSize);               \
+                                                                        \
+               ref_fir_sparse_##suffix(                                 \
+                     &fir_inst_ref,                                     \
+                     (void *) filtering_##suffix##_inputs,              \
+                     (void *) filtering_output_ref,                     \
+                     (void *) filtering_scratch,                        \
+                     blockSize);                                        \
+                                                                        \
+               FILTERING_SNR_COMPARE_INTERFACE(                         \
+                     blockSize,                                         \
+                     output_type)));                                    \
+                                                                        \
+            return JTEST_TEST_PASSED;                                   \
+   }
+
+#define FIR_SPARSE2_DEFINE_TEST(suffix, output_type)                    \
+   JTEST_DEFINE_TEST(arm_fir_sparse_##suffix##_test,                    \
+         arm_fir_sparse_##suffix)                                       \
+   {                                                                    \
+      arm_fir_sparse_instance_##suffix fir_inst_fut = { 0 };            \
+      arm_fir_sparse_instance_##suffix fir_inst_ref = { 0 };            \
+                                                                        \
+      TEMPLATE_DO_ARR_DESC(                                             \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes    \
+            ,                                                           \
+         TEMPLATE_DO_ARR_DESC(                                          \
+               numtaps_idx, uint16_t, numTaps, filtering_numtaps        \
+               ,                                                        \
+              /* Display test parameter values */                       \
+              JTEST_DUMP_STRF("Block Size: %d\n"                        \
+                              "Number of Taps: %d\n"                    \
+                              "Tap Delay: %d\n",                        \
+                              (int)blockSize,                           \
+                              (int)numTaps,                             \
+                              (int)FILTERING_MAX_TAP_DELAY);            \
+                                                                        \
+               /* Initialize the FIR Instances */                       \
+               arm_fir_sparse_init_##suffix(                            \
+                     &fir_inst_fut, numTaps,                            \
+                     (output_type*)filtering_coeffs_##suffix,           \
+                     (void *) filtering_pState,                         \
+                     (int32_t*)filtering_tap_delay,                     \
+                     FILTERING_MAX_TAP_DELAY, blockSize);               \
+                                                                        \
+               JTEST_COUNT_CYCLES(                                      \
+                     arm_fir_sparse_##suffix(                           \
+                           &fir_inst_fut,                               \
+                           (void *) filtering_##suffix##_inputs,        \
+                           (void *) filtering_output_fut,               \
+                           (void *) filtering_scratch,                  \
+                           (void *) filtering_scratch2,                 \
+                           blockSize));                                 \
+                                                                        \
+               arm_fir_sparse_init_##suffix(                            \
+                     &fir_inst_ref, numTaps,                            \
+                     (output_type*)filtering_coeffs_##suffix,           \
+                     (void *) filtering_pState,                         \
+                     (int32_t*)filtering_tap_delay,                     \
+                     FILTERING_MAX_TAP_DELAY, blockSize);               \
+                                                                        \
+               ref_fir_sparse_##suffix(                                 \
+                     &fir_inst_ref,                                     \
+                     (void *) filtering_##suffix##_inputs,              \
+                     (void *) filtering_output_ref,                     \
+                     (void *) filtering_scratch,                        \
+                     (void *) filtering_scratch2,                       \
+                     blockSize);                                        \
+                                                                        \
+               FILTERING_SNR_COMPARE_INTERFACE(                         \
+                     blockSize,                                         \
+                     output_type)));                                    \
+                                                                        \
+            return JTEST_TEST_PASSED;                                   \
+   }
+
+FIR_DEFINE_TEST(f32,,float32_t);
+FIR_DEFINE_TEST(q31,,q31_t);
+FIR_DEFINE_TEST(q15,,q15_t);
+FIR_DEFINE_TEST(q31,_fast,q31_t);
+FIR_DEFINE_TEST(q15,_fast,q15_t);
+FIR_DEFINE_TEST(q7,,q7_t);
+
+FIR_LATTICE_DEFINE_TEST(f32,float32_t);
+FIR_LATTICE_DEFINE_TEST(q31,q31_t);
+FIR_LATTICE_DEFINE_TEST(q15,q15_t);
+
+FIR_INTERPOLATE_DEFINE_TEST(f32,float32_t);
+FIR_INTERPOLATE_DEFINE_TEST(q31,q31_t);
+FIR_INTERPOLATE_DEFINE_TEST(q15,q15_t);
+
+FIR_DECIMATE_DEFINE_TEST(f32,,float32_t);
+FIR_DECIMATE_DEFINE_TEST(q31,,q31_t);
+FIR_DECIMATE_DEFINE_TEST(q15,,q15_t);
+FIR_DECIMATE_DEFINE_TEST(q31,_fast,q31_t);
+FIR_DECIMATE_DEFINE_TEST(q15,_fast,q15_t);
+
+FIR_SPARSE_DEFINE_TEST(f32,float32_t);
+FIR_SPARSE_DEFINE_TEST(q31,q31_t);
+FIR_SPARSE2_DEFINE_TEST(q15,q15_t);
+FIR_SPARSE2_DEFINE_TEST(q7,q7_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(fir_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+   JTEST_TEST_CALL(arm_fir_f32_test);
+   JTEST_TEST_CALL(arm_fir_q31_test);
+   JTEST_TEST_CALL(arm_fir_q15_test);
+   JTEST_TEST_CALL(arm_fir_q7_test);
+   JTEST_TEST_CALL(arm_fir_fast_q31_test);
+   JTEST_TEST_CALL(arm_fir_fast_q15_test);
+
+   JTEST_TEST_CALL(arm_fir_lattice_f32_test);
+   JTEST_TEST_CALL(arm_fir_lattice_q31_test);
+   JTEST_TEST_CALL(arm_fir_lattice_q15_test);
+
+   JTEST_TEST_CALL(arm_fir_interpolate_f32_test);
+   JTEST_TEST_CALL(arm_fir_interpolate_q31_test);
+   JTEST_TEST_CALL(arm_fir_interpolate_q15_test);
+
+   JTEST_TEST_CALL(arm_fir_decimate_f32_test);
+   JTEST_TEST_CALL(arm_fir_decimate_q31_test);
+   JTEST_TEST_CALL(arm_fir_decimate_q15_test);
+   JTEST_TEST_CALL(arm_fir_decimate_fast_q31_test);
+   JTEST_TEST_CALL(arm_fir_decimate_fast_q15_test);
+
+   JTEST_TEST_CALL(arm_fir_sparse_f32_test);
+   JTEST_TEST_CALL(arm_fir_sparse_q31_test);
+   JTEST_TEST_CALL(arm_fir_sparse_q15_test);
+   JTEST_TEST_CALL(arm_fir_sparse_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c

+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+#define IIR_DEFINE_TEST(suffix, output_type)                                              \
+   JTEST_DEFINE_TEST(arm_iir_lattice_##suffix##_test,                                     \
+         arm_iir_lattice_##suffix)                                                        \
+   {                                                                                      \
+      arm_iir_lattice_instance_##suffix iir_inst_fut = { 0 };                             \
+      arm_iir_lattice_instance_##suffix iir_inst_ref = { 0 };                             \
+                                                                                          \
+      TEMPLATE_DO_ARR_DESC(                                                               \
+            blocksize_idx, uint32_t, blockSize, filtering_blocksizes                      \
+            ,                                                                             \
+         TEMPLATE_DO_ARR_DESC(                                                            \
+               numstages_idx, uint16_t, numStages, filtering_numstages                    \
+               ,                                                                          \
+              /* Display test parameter values */                                         \
+              JTEST_DUMP_STRF("Block Size: %d\n"                                          \
+                              "Number of Stages: %d\n",                                   \
+                              (int)blockSize,                                             \
+                              (int)numStages);                                            \
+                                                                                          \
+               /* Initialize the IIR Instances */                                         \
+               arm_iir_lattice_init_##suffix(                                             \
+                     &iir_inst_fut, numStages, (output_type*)filtering_coeffs_b_##suffix, \
+                     (output_type*)filtering_coeffs_c_##suffix,                           \
+                     (void *) filtering_pState, blockSize);                               \
+                                                                                          \
+               JTEST_COUNT_CYCLES(                                                        \
+                     arm_iir_lattice_##suffix(                                            \
+                           &iir_inst_fut,                                                 \
+                           (void *) filtering_##suffix##_inputs,                          \
+                           (void *) filtering_output_fut,                                 \
+                           blockSize));                                                   \
+                                                                                          \
+               arm_iir_lattice_init_##suffix(                                             \
+                     &iir_inst_ref, numStages, (output_type*)filtering_coeffs_b_##suffix, \
+                     (output_type*)filtering_coeffs_c_##suffix,                           \
+                     (void *) filtering_pState, blockSize);                               \
+                                                                                          \
+               ref_iir_lattice_##suffix(                                                  \
+                     &iir_inst_ref,                                                       \
+                     (void *) filtering_##suffix##_inputs,                                \
+                     (void *) filtering_output_ref,                                       \
+                     blockSize);                                                          \
+                                                                                          \
+               FILTERING_SNR_COMPARE_INTERFACE(                                           \
+                     blockSize,                                                           \
+                     output_type)));                                                      \
+                                                                                          \
+            return JTEST_TEST_PASSED;                                                     \
+   }
+
+IIR_DEFINE_TEST(f32, float32_t);
+IIR_DEFINE_TEST(q31, q31_t);
+IIR_DEFINE_TEST(q15, q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(iir_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+   JTEST_TEST_CALL(arm_iir_lattice_f32_test);
+   JTEST_TEST_CALL(arm_iir_lattice_q31_test);
+   JTEST_TEST_CALL(arm_iir_lattice_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c

+#include "jtest.h"
+#include "filtering_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "filtering_templates.h"
+#include "type_abbrev.h"
+
+static const float32_t mu_f32 = 0.00854f;//1.0f;
+static const float32_t mu2_f32 = 1.0f;
+static const q31_t mu_q31 = 0x7fffffff;
+static const q15_t mu_q15 = 0x7fff;
+
+#define LMS_DEFINE_TEST(suffix, config_suffix, output_type, mu)                        \
+   JTEST_DEFINE_TEST(arm_lms##config_suffix##_##suffix##_test,                         \
+         arm_lms##config_suffix##_##suffix)                                            \
+   {                                                                                   \
+      arm_lms##config_suffix##_instance_##suffix lms_inst_fut = { 0 };                 \
+      arm_lms##config_suffix##_instance_##suffix lms_inst_ref = { 0 };                 \
+      arm_fir_instance_##suffix fir_inst = { 0 };                                      \
+      uint32_t i;                                                                      \
+                                                                                       \
+      TEMPLATE_DO_ARR_DESC(                                                            \
+            blocksize_idx, uint32_t, blockSize, lms_blocksizes                         \
+            ,                                                                          \
+         TEMPLATE_DO_ARR_DESC(                                                         \
+               numtaps_idx, uint16_t, numTaps, filtering_numtaps                       \
+               ,                                                                       \
+               /* Initialize the FIR Instances */                                      \
+               arm_fir_init_##suffix(                                                  \
+                     &fir_inst, numTaps,                                               \
+                     (output_type*)filtering_coeffs_##suffix,                          \
+                     (void *) filtering_pState, blockSize);                            \
+                                                                                       \
+               ref_fir_##suffix(                                                       \
+                     &fir_inst,                                                        \
+                     (void *) filtering_##suffix##_inputs,                             \
+                     (void *) filtering_input_lms,                                     \
+                     blockSize);                                                       \
+                                                                                       \
+               for(i=0;i<numTaps;i++)                                                  \
+               {                                                                       \
+                  *((output_type*)filtering_coeffs_lms + i) = (output_type)0;          \
+               }                                                                       \
+                                                                                       \
+               for(i=0;i<blockSize;i++)                                                \
+               {                                                                       \
+                  /* scaled down so that lms will converge           */                \
+                  /* scaled down by almost the max of the abs(input) */                \
+                  *((output_type*)filtering_input_lms + i) =                           \
+                        *((output_type*)filtering_input_lms + i) / 200.0f;             \
+                                                                                       \
+                  *((output_type*)filtering_output_f32_fut + i) =                      \
+                        *((output_type*)filtering_##suffix##_inputs + i) / 200.0f;     \
+               }                                                                       \
+                                                                                       \
+               /* Display test parameter values */                                     \
+               JTEST_DUMP_STRF("Block Size: %d\n"                                      \
+                               "Number of Taps: %d\n",                                 \
+                               (int)blockSize,                                         \
+                               (int)numTaps);                                          \
+                                                                                       \
+               /* Initialize the LMS Instances */                                      \
+               arm_lms##config_suffix##_init_##suffix(                                 \
+                     &lms_inst_fut, numTaps,                                           \
+                     (output_type*)filtering_coeffs_lms,                               \
+                     (void *) filtering_pState, mu, blockSize);                        \
+                                                                                       \
+               JTEST_COUNT_CYCLES(                                                     \
+                     arm_lms##config_suffix##_##suffix(                                \
+                           &lms_inst_fut,                                              \
+                           (void *) filtering_output_f32_fut,                          \
+                           (void *) filtering_input_lms,                               \
+                           (void *) filtering_output_fut,                              \
+                           (void *) ((output_type*)filtering_output_fut+blockSize),    \
+                           blockSize));                                                \
+                                                                                       \
+               for(i=0;i<numTaps;i++)                                                  \
+               {                                                                       \
+                  *((output_type*)filtering_coeffs_lms + i) = (output_type)0;          \
+               }                                                                       \
+                                                                                       \
+               arm_lms##config_suffix##_init_##suffix(                                 \
+                     &lms_inst_ref, numTaps,                                           \
+                     (output_type*)filtering_coeffs_lms,                               \
+                     (void *) filtering_pState, mu, blockSize);                        \
+                                                                                       \
+               ref_lms##config_suffix##_##suffix(                                      \
+                     &lms_inst_ref,                                                    \
+                     (void *) filtering_output_f32_fut,                                \
+                     (void *) filtering_input_lms,                                     \
+                     (void *) filtering_output_ref,                                    \
+                     (void *) ((output_type*)filtering_output_fut+blockSize),          \
+                     blockSize);                                                       \
+                                                                                       \
+               FILTERING_SNR_COMPARE_INTERFACE(                                        \
+                     blockSize,                                                        \
+                     output_type)));                                                   \
+                                                                                       \
+            return JTEST_TEST_PASSED;                                                  \
+   }
+
+#define LMS_WITH_POSTSHIFT_DEFINE_TEST(suffix, config_suffix, output_type)             \
+   JTEST_DEFINE_TEST(arm_lms##config_suffix##_##suffix##_test,                         \
+         arm_lms##config_suffix##_##suffix)                                            \
+   {                                                                                   \
+      arm_lms##config_suffix##_instance_##suffix lms_inst_fut = { 0 };                 \
+      arm_lms##config_suffix##_instance_##suffix lms_inst_ref = { 0 };                 \
+      arm_fir_instance_##suffix fir_inst = { 0 };                                      \
+      uint32_t i;                                                                      \
+                                                                                       \
+      TEMPLATE_DO_ARR_DESC(                                                            \
+            blocksize_idx, uint32_t, blockSize, lms_blocksizes                         \
+            ,                                                                          \
+         TEMPLATE_DO_ARR_DESC(                                                         \
+               numtaps_idx, uint16_t, numTaps, filtering_numtaps                       \
+               ,                                                                       \
+               TEMPLATE_DO_ARR_DESC(                                                   \
+                     postshifts_idx, uint8_t, postShift, filtering_postshifts          \
+                     ,                                                                 \
+                  /* Initialize the FIR Instances */                                   \
+                  arm_fir_init_##suffix(                                               \
+                        &fir_inst, numTaps,                                            \
+                        (output_type*)filtering_coeffs_##suffix,                       \
+                        (void *) filtering_pState, blockSize);                         \
+                                                                                       \
+                  ref_fir_##suffix(                                                    \
+                        &fir_inst,                                                     \
+                        (void *) filtering_##suffix##_inputs,                          \
+                        (void *) filtering_input_lms,                                  \
+                        blockSize);                                                    \
+                                                                                       \
+                  for(i=0;i<numTaps;i++)                                               \
+                  {                                                                    \
+                     *((output_type*)filtering_coeffs_lms + i) = (output_type)0;       \
+                  }                                                                    \
+                                                                                       \
+                  for(i=0;i<blockSize;i++)                                             \
+                  {                                                                    \
+                     /* scaled down so that lms will converge */                       \
+                     /* scaled down by log2(numTaps) bits     */                       \
+                     *((output_type*)filtering_output_f32_fut + i) =                   \
+                           *((output_type*)filtering_##suffix##_inputs + i) >> 6;      \
+                  }                                                                    \
+                                                                                       \
+                  /* Display test parameter values */                                  \
+                  JTEST_DUMP_STRF("Block Size: %d\n"                                   \
+                                  "Number of Taps: %d\n"                               \
+                                  "Post Shift: %d\n",                                  \
+                                  (int)blockSize,                                      \
+                                  (int)numTaps,                                        \
+                                  (int)postShift);                                     \
+                                                                                       \
+                  /* Initialize the LMS Instances */                                   \
+                  arm_lms##config_suffix##_init_##suffix(                              \
+                        &lms_inst_fut, numTaps,                                        \
+                        (output_type*)filtering_coeffs_lms,                            \
+                        (void *) filtering_pState, mu_##suffix, blockSize, postShift); \
+                                                                                       \
+                  JTEST_COUNT_CYCLES(                                                  \
+                        arm_lms##config_suffix##_##suffix(                             \
+                              &lms_inst_fut,                                           \
+                              (void *) filtering_output_f32_fut,                       \
+                              (void *) filtering_input_lms,                            \
+                              (void *) filtering_output_fut,                           \
+                              (void *) ((output_type*)filtering_output_fut+blockSize), \
+                              blockSize));                                             \
+                                                                                       \
+                  for(i=0;i<numTaps;i++)                                               \
+                  {                                                                    \
+                     *((output_type*)filtering_coeffs_lms + i) = (output_type)0;       \
+                  }                                                                    \
+                                                                                       \
+                  arm_lms##config_suffix##_init_##suffix(                              \
+                        &lms_inst_ref, numTaps,                                        \
+                        (output_type*)filtering_coeffs_lms,                            \
+                        (void *) filtering_pState, mu_##suffix, blockSize, postShift); \
+                                                                                       \
+                  ref_lms##config_suffix##_##suffix(                                   \
+                        &lms_inst_ref,                                                 \
+                        (void *) filtering_output_f32_fut,                             \
+                        (void *) filtering_input_lms,                                  \
+                        (void *) filtering_output_ref,                                 \
+                        (void *) ((output_type*)filtering_output_ref+blockSize),       \
+                        blockSize);                                                    \
+                                                                                       \
+                  FILTERING_SNR_COMPARE_INTERFACE(                                     \
+                        blockSize,                                                     \
+                        output_type))));                                               \
+                                                                                       \
+            return JTEST_TEST_PASSED;                                                  \
+   }
+
+LMS_DEFINE_TEST(f32,,float32_t, mu_f32);
+LMS_WITH_POSTSHIFT_DEFINE_TEST(q31,,q31_t);
+LMS_WITH_POSTSHIFT_DEFINE_TEST(q15,,q15_t);
+
+LMS_DEFINE_TEST(f32,_norm,float32_t, mu2_f32);
+LMS_WITH_POSTSHIFT_DEFINE_TEST(q31,_norm,q31_t);
+LMS_WITH_POSTSHIFT_DEFINE_TEST(q15,_norm,q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(lms_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+   JTEST_TEST_CALL(arm_lms_f32_test);
+   JTEST_TEST_CALL(arm_lms_q31_test);
+   JTEST_TEST_CALL(arm_lms_q15_test);
+
+   JTEST_TEST_CALL(arm_lms_norm_f32_test);
+   JTEST_TEST_CALL(arm_lms_norm_q31_test);
+   JTEST_TEST_CALL(arm_lms_norm_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.c

+#include "jtest.h"
+#include "ref.h"
+#include "arr_desc.h"
+#include "intrinsics_templates.h"
+#include "intrinsics_test_data.h"
+#include "type_abbrev.h"
+
+INTRINSICS_TEST_TEMPLATE_ELT2(__QADD8, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QSUB8, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QADD16, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SHADD16, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QSUB16, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SHSUB16, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QASX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SHASX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QSAX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SHSAX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SMUSDX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SMUADX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QADD, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__QSUB, q31);
+INTRINSICS_TEST_TEMPLATE_ELT3(__SMLAD, q31);
+INTRINSICS_TEST_TEMPLATE_ELT3(__SMLADX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT3(__SMLSDX, q31);
+INTRINSICS_TEST_TEMPLATE_ELT4(__SMLALD, q31, q63);
+INTRINSICS_TEST_TEMPLATE_ELT4(__SMLALDX, q31, q63);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SMUAD, q31);
+INTRINSICS_TEST_TEMPLATE_ELT2(__SMUSD, q31);
+INTRINSICS_TEST_TEMPLATE_ELT1(__SXTB16, q31);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(intrinsics_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+   JTEST_TEST_CALL(__QADD8_test);
+   JTEST_TEST_CALL(__QSUB8_test);
+   JTEST_TEST_CALL(__QADD16_test);
+   JTEST_TEST_CALL(__SHADD16_test);
+   JTEST_TEST_CALL(__QSUB16_test);
+   JTEST_TEST_CALL(__SHSUB16_test);
+   JTEST_TEST_CALL(__QASX_test);
+   JTEST_TEST_CALL(__SHASX_test);
+   JTEST_TEST_CALL(__QSAX_test);
+   JTEST_TEST_CALL(__SHSAX_test);
+   JTEST_TEST_CALL(__SMUSDX_test);
+   JTEST_TEST_CALL(__SMUADX_test);
+   JTEST_TEST_CALL(__QADD_test);
+   JTEST_TEST_CALL(__QSUB_test);
+   JTEST_TEST_CALL(__SMLAD_test);
+   JTEST_TEST_CALL(__SMLADX_test);
+   JTEST_TEST_CALL(__SMLSDX_test);
+   JTEST_TEST_CALL(__SMLALD_test);
+   JTEST_TEST_CALL(__SMLALDX_test);
+   JTEST_TEST_CALL(__SMUAD_test);
+   JTEST_TEST_CALL(__SMUSD_test);
+   JTEST_TEST_CALL(__SXTB16_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.c

+#include "intrinsics_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+q63_t intrinsics_output_fut[INTRINSICS_MAX_LEN] = {0};
+q63_t intrinsics_output_ref[INTRINSICS_MAX_LEN] = {0};
+float32_t intrinsics_output_f32_fut[INTRINSICS_MAX_LEN] = {0};
+float32_t intrinsics_output_f32_ref[INTRINSICS_MAX_LEN] = {0};
+
+const q63_t intrinsics_q63_inputs[INTRINSICS_MAX_LEN] =
+{
+    0xF7D2D6F5414A5524, 0x5297DAF44CAB5A17, 0x54129B222D6F5B56, 0x54141F6F7DAF4E3B, 0x44C414A529B226EB, 0x22D4CAB541F6F6A ,
+    0x6053A44325CE38BF, 0x33D055403A970AFA, 0x0133D0603A44382A, 0x32513D5605540F8 , 0x03A25CE33D060524, 0x03A3A97013D56570,
+    0x3402674117D7791D, 0x72140A667FE0438C, 0x439218E426741841, 0x11739FF340A66E54, 0x67F17D77218E4386, 0x4267FE0439FF3726,
+    0x46C411420DC177CA, 0x7156C147702F2CF5, 0x26615F6441142FF1, 0x20D662C46C1476AB, 0x7700DC1715F640DD, 0x441702F2662C4E49,
+    0x50D4F8B538055E7E, 0x5570D192770871FE, 0x725576474F8B5360, 0x538258550D1928A0, 0x2773805557647821, 0x74F77087258558CF,
+    0x05066D230C0C604D, 0x63650FA350A46C19, 0x66C3646266D2370D, 0x30C6CE0050FA359A, 0x3500C0C636462E24, 0x26650A466CE00F5C,
+    0x21E3B72166D40948, 0x0731EB61355B5831, 0x577733943B72150A, 0x166773F21EB61530, 0x13566D4073394127, 0x43B355B5773F26F4,
+    0x7221CF5118052980, 0x27A22AD1038D6587, 0x67C7A8121CF517F4, 0x1187CDC722AD1691, 0x103180527A812473, 0x21C038D67CDC7D7F,
+    0x21A0FD604A5110D0, 0x1201A2156D895BB9, 0x53D20EB60FD60F35, 0x04A3DE621A215530, 0x56D4A51120EB6DDA, 0x60F6D8953DE62516,
+    0x02C61E17250123E1, 0x26D2CBB35ED813C8, 0x15B6D35061E175B1, 0x7255B1402CBB32F3, 0x35E250126D350907, 0x0615ED815B140D7E,
+    0x126418B76EAE272D, 0x23C26BB13E221841, 0x1243CF01418B7B88, 0x76E24DB126BB1B80, 0x13E6EAE23CF010E4, 0x1413E22124DB166C,
+    0x1634700479AB7E42, 0x74163F5662DF28D1, 0x246419E047004665, 0x47946BE163F56FC6, 0x66279AB7419E0C75, 0x04762DF246BE1F38,
+    0x63F5CE12243239B2, 0x31F3F574758D03E0, 0x0711F4455CE12926, 0x22471D563F574B74, 0x475243231F4458E2, 0x55C758D071D5639 ,
+    0x34806EF703A17B49, 0x77D48D32173A7C76, 0x70F7D3E306EF7531, 0x7030F2F348D32F34, 0x21703A177D3E3063, 0x306173A70F2F3549,
+    0x54426F835C314C9 , 0x42E447B118CB6B6D, 0x6502E32326F83697, 0x35C50745447B1E9C, 0x1185C3142E323A33, 0x32618CB650745715,
+    0x51D4891001AC5746, 0x5601DA36655A4E04, 0x42060E624891060F, 0x00120BF51DA36B4F, 0x66501AC560E6227F, 0x248655A420BF5EB4,
+    0x1154156550B3225B, 0x2181540540C10544, 0x02318586415656C , 0x550236A115405EAE, 0x54050B32185863E1, 0x64140C10236A1C4E,
+    0x44E7736608BD21F9, 0x2614EDF52ACF7A68, 0x752617A1773665E5, 0x608524F44EDF5F66, 0x52A08BD2617A1610, 0x1772ACF7524F4968,
+    0x06A24DC242D006CD, 0x0376A4F55F000079, 0x01D3706424DC2447, 0x2421DE706A4F5599, 0x55F42D0037064D4A, 0x4245F0001DE70608,
+    0x44018061233A2EE5, 0x22440795137E488E, 0x44424A8118061B7B, 0x12344CE44079569D, 0x513233A224A817D5, 0x118137E444CE48F5,
+    0x41D71AD7575F7883, 0x73C1D4A522406802, 0x6333CBC771AD70BB, 0x757335841D4A5D79, 0x522575F73CBC7CE4, 0x77122406335840D8,
+    0x3333D19605792E47, 0x233331A427AD2C05, 0x213330353D196EAB, 0x60513D93331A40AF, 0x4270579233035831, 0x53D27AD213D93987,
+    0x0135DC437C542094, 0x25C13796045F317E, 0x37D5C2015DC43F8B, 0x37C7DD501379650C, 0x6047C5425C20193F, 0x15D045F37DD50298,
+    0x5275C8A71D482B82, 0x210272914A6B6062, 0x63510E165C8A757B, 0x71D355A5272917C1, 0x14A1D48210E16FBC, 0x65C4A6B6355A5882,
+    0x1757DF7F66F86A35, 0x61A758A6604555A1, 0x5531A1137DF7FBB , 0xF6653541758A6216, 0x66066F861A113463, 0x37D6045553541BAD,
+    0x04E1F05221576756, 0x6554EA63483B6D8D, 0x67B55B841F052FCC, 0x2217B2E04EA63DFB, 0x3482157655B84677, 0x41F483B67B2E04F2,
+    0x41D46029787A796C, 0x71A1DB2204A12CD3, 0x2061A8C746029BD , 0x978061E41DB22DD8, 0x204787A71A8C7F28, 0x74604A12061E452E,
+    0x66B73357132D3F78, 0x3626BBB076525852, 0x53F6253673357BBA, 0x7133F6B66BBB0A58, 0x076132D362536AFA, 0x673765253F6B65EF,
+    0x55F66B026DC57B58, 0x7325FF601EB718CE, 0x17F3247766B02740, 0x26D7FF355FF60B47, 0x01E6DC5732477B8F, 0x7661EB717FF35302,
+    0x7206FF9529FD3E40, 0x34720182475A43D1, 0x44C47E076FF9528A, 0x5294CF572018209D, 0x24729FD347E079C9, 0x76F475A44CF576D3,
+    0x2512340428074E34, 0x42551CE35D6F58ED, 0x56425297234045D1, 0x4286443251CE35F9, 0x35D2807425297896, 0x7235D6F5644320FE,
+    0x04E701D50F4449A9, 0x4714E09454C361C6, 0x661718F0701D52F1, 0x50F615404E094820, 0x4540F444718F0810, 0x07054C3661540689,
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+    0x7640AC043F30596E, 0x51E641973E2A527B, 0x5211ECC30AC04220, 0x43F21447641979A3, 0x73E3F3051ECC3B89, 0x30A3E2A521447BC1,
+    0x157299E54E8F2E26, 0x21D57C940C5A1D90, 0x1761D486299E5467, 0x54E76F3157C947E3, 0x40C4E8F21D4865ED, 0x6290C5A176F31C3D,
+    0x05C6FFB34EE81CDF, 0x1305C8233479195E, 0x147300F76FFB3AE1, 0x34E479405C82398 , 0x3344EE81300F7364, 0x76F3479147940AFA,
+    0xF3A224A33B853E3E, 0x3223A674598C440D, 0x42E22880224A3D89, 0x33B2E77F3A674204, 0x4593B85322880A38, 0x022598C42E77F2D ,
+    0x6091FE9022841C9C, 0x12D093354F0609C3, 0x07E2D6B61FE90922, 0x0227EDB609335017, 0x54F228412D6B69A7, 0x61F4F0607EDB63F9,
+    0xE2524BE1099A74EF, 0x716251D21F9F1B40, 0x12816AC524BE17E8, 0x10928D7E251D2F7A, 0x21F099A716AC50D3, 0x5241F9F128D7ED6 ,
+    0x36430DF66D193443, 0x36364FF676156F1B, 0x67463DB230DF6A4E, 0x66D7435364FF6794, 0x6766D19363DB2C9A, 0x2307615674353022,
+    0x16742501556E025C, 0x070675A123802AF9, 0x27F70B22425018A4, 0x1557FB01675A18BB, 0x123556E070B227B9, 0x242238027FB01BF ,
+    0x14F6574563E7910 , 0x9524F6E36C661591, 0x11E52B3265745D2B, 0x5631E6A14F6E379D, 0x36C63E7952B32FAC, 0x2656C6611E6A1101,
+    0x34B469701DE22385, 0x2544BAB42338191F, 0x17854EB4469704B6, 0x01D783934BAB4599, 0x4231DE2254EB4809, 0x4462338178393E6D,
+    0x02D288D5550017DD, 0x1202D52639B120E1, 0x24E20D22288D52D3, 0x5554E1202D52668C, 0x6395500120D22A68, 0x22839B124E1207D1,
+    0x734251773FCC0EFE, 0x05A34BF547F37E64, 0x76F5A8D325177A90, 0x73F6F72734BF5D4D, 0x5473FCC05A8D3DCE, 0x32547F376F7275A8,
+    0x70A64DB56BEA2655, 0x22C0A4D42A1810FC, 0x1712C40264DB593A, 0x56B71C070A4D4BC0, 0x42A6BEA22C402E93, 0x2642A18171C077F9,
+    0x458752F16F0C4577, 0x42C582E370412414, 0x24D2C455752F1DC1, 0x16F4DCD4582E38EA, 0x3706F0C42C455F7B, 0x575704124DCD4EDB,
+    0x53D4FCA112BC2696, 0x2503D5E77B037135, 0x736502F44FCA1F8C, 0x112361653D5E75F6, 0x77B12BC2502F41B0, 0x44F7B037361653F1,
+    0x64657E702E5B0E31, 0x047467B320266B19, 0x61F4703257E703D7, 0x02E1F776467B3E00, 0x3202E5B047032BA3, 0x257202661F776B9C,
+    0x07D1BD5062570A84, 0x07F7D0A27EC75B48, 0x5297FCC21BD5012 , 0x062291307D0A2D5D, 0x27E625707FCC29F2, 0x21B7EC75291304B6,
+    0xE3A7D12719D558ED, 0x55F3ADE047551C8 , 0x1255F7417D12738F, 0x71925D2E3ADE0892, 0x04719D555F741997, 0x17D4755125D2E2F ,
+    0x65415E922B9F2269, 0x227544375C134FED, 0x456272D315E92399, 0x22B5618654437F4E, 0x75C2B9F2272D32AB, 0x3155C13456186AA1,
+    0x8462A8717E4D355C, 0x32C4637A234D7836, 0x75F2C1832A871760, 0x17E5FC784637A94 , 0xA237E4D32C183207, 0x32A234D75FC78B3 ,
+    0x34E6C9F47F10621E, 0x6624E3F1276966B2, 0x62562BA26C9F4A11, 0x47F25F234E3F182C, 0x1277F10662BA2EF5, 0x26C2769625F239CD,
+    0x63F0AC1573D63FED, 0x3733F3D3636E1F5E, 0x135738320AC15A0E, 0x57335C363F3D33EB, 0x36373D63738326EA, 0x20A636E135C366B1,
+    0x642711A14D476E86, 0x67E426A402F63208, 0x3757E4D1711A1FC1, 0x14D75E46426A4396, 0x4024D4767E4D1B93, 0x17102F6375E46DB7,
+    0x60A7AD242F3C44A7, 0x4490A56351A56F5C, 0x64C499527AD2463D, 0x42F4C4B60A5639CA, 0x3512F3C449952C78, 0x27A51A564C4B64F6,
+    0x14B438673AFE7F8D, 0x7554BC1466993D04, 0x36855A8743867F37, 0x73A681A14BC146C2, 0x4663AFE755A875EC, 0x74366993681A1A75,
+    0x61820F7730A67E1B, 0x773189184A4A7D0C, 0x7547389720F77993, 0x730542661891805 , 0x84A30A67738976AD, 0x7204A4A7542667D6,
+    0x6442BF173C5C6EBF, 0x668447C34499187F, 0x17A68D842BF17C97, 0x73C7AAB6447C317F, 0x3443C5C668D8419C, 0x42B449917AAB6456,
+    0x43D09163421B4F29, 0x41A3D72A76740F9C, 0x0751AD5409163B8D, 0x342754943D72AAB , 0xA76421B41AD54DD7, 0x40976740754946EE,
+    0x654105637317342B, 0x30C54BB4218546D4, 0x45D0CE6310563DA7, 0x3735D14654BB4CCE, 0x421731730CE63E46, 0x310218545D146234,
+    0x40709D7233BE6C63, 0x63607C36325044E5, 0x42D3655309D72335, 0x2332DFA407C36BA , 0x63233BE6365530CC, 0x309325042DFA448C,
+    0x312150271663516F, 0x53C1253259B00AA , 0x0493CEF0150274EA, 0x716492F312532D4A, 0x259166353CEF002D, 0x01559B00492F3DA5,
+    0x72F14A10263A2574, 0x2682F6276F8005C2, 0x0266829314A10651, 0x026269872F627ABA, 0x76F263A268293238, 0x3146F80026987646,
+    0x12B59B1552590516, 0x0532B2A410144D36, 0x4275395359B151B9, 0x552278512B2A4F05, 0x4105259053953699, 0x3591014427851C75,
+    0xF4F32843180646F3, 0x54718F4F2E970306, 0x6623953632843145, 0x318D315E18F4FE8F
+};
+
+/* The source data is random across the q63_t range. Accessing it by word should
+   remain random. */
+const q31_t * intrinsics_q31_inputs = (q31_t *) intrinsics_q63_inputs;

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.c

+#include "jtest.h"
+#include "all_tests.h"
+#include "arm_math.h"
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+asm(" .global __ARM_use_no_argv\n");
+#endif
+
+
+void debug_init(void)
+{
+    uint32_t * SHCSR_ptr = (uint32_t *) 0xE000ED24; /* System Handler Control and State Register */
+    *SHCSR_ptr |= 0x70000;             /* Enable  UsageFault, BusFault, and MemManage fault*/
+}
+
+int main(void)
+{
+    debug_init();
+
+    JTEST_INIT();               /* Initialize test framework. */
+
+    JTEST_GROUP_CALL(all_tests); /* Run all tests. */
+
+    JTEST_ACT_EXIT_FW();        /* Exit test framework.  */
+    while (1);                   /* Never return. */
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date:        29. November 2010
+* $Revision:    V1.0.3
+*
+* Project:      CMSIS DSP Library
+*
+* Title:        math_helper.c
+*
+* Description:  Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.3 2010/11/29
+*    Re-organized the CMSIS folders and updated documentation.
+*
+* Version 1.0.2 2010/11/11
+*    Documentation updated.
+*
+* Version 1.0.1 2010/10/05
+*    Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20
+*    Production release and review comments incorporated.
+*
+* Version 0.0.7  2010/06/10
+*    Misra-C changes done
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+*       Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+*       Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief  Caluclation of SNR
+ * @param  float*   Pointer to the reference buffer
+ * @param  float*   Pointer to the test buffer
+ * @param  uint32_t     total number of samples
+ * @return float    SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+  float EnergySignal = 0.0, EnergyError = 0.0;
+  uint32_t i;
+  float SNR;
+  int temp;
+  int *test;
+
+  for (i = 0; i < buffSize; i++)
+    {
+      /* Checking for a NAN value in pRef array */
+      test =   (int *)(&pRef[i]);
+      temp =  *test;
+
+      if (temp == 0x7FC00000)
+      {
+            return(0);
+      }
+
+      /* Checking for a NAN value in pTest array */
+      test =   (int *)(&pTest[i]);
+      temp =  *test;
+
+      if (temp == 0x7FC00000)
+      {
+            return(0);
+      }
+      EnergySignal += pRef[i] * pRef[i];
+      EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+    }
+
+    /* Checking for a NAN value in EnergyError */
+    test =   (int *)(&EnergyError);
+    temp =  *test;
+
+    if (temp == 0x7FC00000)
+    {
+        return(0);
+    }
+
+
+  SNR = 10 * log10f (EnergySignal / EnergyError);
+
+	return (SNR);
+
+}
+
+
+
+double arm_snr_f64(double *pRef, double *pTest, uint32_t buffSize)
+{
+  double EnergySignal = 0.0, EnergyError = 0.0;
+  uint32_t i;
+  double SNR;
+  int temp;
+  int *test;
+
+  for (i = 0; i < buffSize; i++)
+    {
+      /* Checking for a NAN value in pRef array */
+      test =   (int *)(&pRef[i]);
+      temp =  *test;
+
+      if (temp == 0x7FC00000)
+      {
+            return(0);
+      }
+
+      /* Checking for a NAN value in pTest array */
+      test =   (int *)(&pTest[i]);
+      temp =  *test;
+
+      if (temp == 0x7FC00000)
+      {
+            return(0);
+      }
+      EnergySignal += pRef[i] * pRef[i];
+      EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+    }
+
+    /* Checking for a NAN value in EnergyError */
+    test =   (int *)(&EnergyError);
+    temp =  *test;
+
+    if (temp == 0x7FC00000)
+    {
+        return(0);
+    }
+
+
+  SNR = 10 * log10 (EnergySignal / EnergyError);
+
+  return (SNR);
+
+}
+
+/**
+ * @brief  Provide guard bits for Input buffer
+ * @param  q15_t*       Pointer to input buffer
+ * @param  uint32_t     blockSize
+ * @param  uint32_t     guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+                            uint32_t guard_bits)
+{
+  uint32_t i;
+
+  for (i = 0; i < blockSize; i++)
+    {
+      input_buf[i] = input_buf[i] >> guard_bits;
+    }
+}
+
+/**
+ * @brief  Converts float to fixed in q12.20 format
+ * @param  uint32_t     number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+      /* 1048576.0f corresponds to pow(2, 20) */
+      pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 1.0)
+        {
+          pOut[i] = 0x000FFFFF;
+        }
+    }
+}
+
+/**
+ * @brief  Compare MATLAB Reference Output and ARM Test output
+ * @param  q15_t*   Pointer to Ref buffer
+ * @param  q15_t*   Pointer to Test buffer
+ * @param  uint32_t     number of samples in the buffer
+ * @return none
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
+{
+  uint32_t i;
+  int32_t diff, diffCrnt = 0;
+  uint32_t maxDiff = 0;
+
+  for (i = 0; i < numSamples; i++)
+  {
+    diff = pIn[i] - pOut[i];
+    diffCrnt = (diff > 0) ? diff : -diff;
+
+    if (diffCrnt > maxDiff)
+    {
+        maxDiff = diffCrnt;
+    }
+  }
+
+  return(maxDiff);
+}
+
+/**
+ * @brief  Compare MATLAB Reference Output and ARM Test output
+ * @param  q31_t*   Pointer to Ref buffer
+ * @param  q31_t*   Pointer to Test buffer
+ * @param  uint32_t     number of samples in the buffer
+ * @return none
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+  uint32_t i;
+  int32_t diff, diffCrnt = 0;
+  uint32_t maxDiff = 0;
+
+  for (i = 0; i < numSamples; i++)
+  {
+    diff = pIn[i] - pOut[i];
+    diffCrnt = (diff > 0) ? diff : -diff;
+
+    if (diffCrnt > maxDiff)
+    {
+        maxDiff = diffCrnt;
+    }
+  }
+
+  return(maxDiff);
+}
+
+/**
+ * @brief  Provide guard bits for Input buffer
+ * @param  q31_t*   Pointer to input buffer
+ * @param  uint32_t     blockSize
+ * @param  uint32_t     guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+                                 uint32_t blockSize,
+                                 uint32_t guard_bits)
+{
+  uint32_t i;
+
+  for (i = 0; i < blockSize; i++)
+    {
+      input_buf[i] = input_buf[i] >> guard_bits;
+    }
+}
+
+/**
+ * @brief  Provide guard bits for Input buffer
+ * @param  q31_t*   Pointer to input buffer
+ * @param  uint32_t     blockSize
+ * @param  uint32_t     guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+                                uint32_t blockSize,
+                                uint32_t guard_bits)
+{
+  uint32_t i;
+
+  for (i = 0; i < blockSize; i++)
+    {
+      input_buf[i] = input_buf[i] >> guard_bits;
+    }
+}
+
+
+
+/**
+ * @brief  Caluclates number of guard bits
+ * @param  uint32_t     number of additions
+ * @return none
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+  uint32_t i = 1, j = 0;
+
+  if (num_adds == 1)
+    {
+      return (0);
+    }
+
+  while (i < num_adds)
+    {
+      i = i * 2;
+      j++;
+    }
+
+  return (j);
+}
+
+/**
+ * @brief  Converts Q15 to floating-point
+ * @param  uint32_t     number of samples in the buffer
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t * pIn,
+                           uint32_t numSamples,
+                           uint32_t guard_bits)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+      pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+    }
+}
+
+/**
+ * @brief  Calculates pow(2, numShifts)
+ * @param  uint32_t     number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+  uint32_t i, val = 1;
+
+  for (i = 0; i < numShifts; i++)
+    {
+      val = val * 2;
+    }
+
+  return(val);
+}
+
+
+
+/**
+ * @brief  Converts float to fixed q14
+ * @param  uint32_t     number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t * pOut,
+                       uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+      /* 16384.0f corresponds to pow(2, 14) */
+      pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 2.0)
+        {
+          pOut[i] = 0x7FFF;
+        }
+
+    }
+
+}
+
+
+/**
+ * @brief  Converts float to fixed q30 format
+ * @param  uint32_t     number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut,
+                       uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+      /* 1073741824.0f corresponds to pow(2, 30) */
+      pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 2.0)
+        {
+          pOut[i] = 0x7FFFFFFF;
+        }
+    }
+}
+
+/**
+ * @brief  Converts float to fixed q30 format
+ * @param  uint32_t     number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t * pOut,
+                       uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+      /* 1073741824.0f corresponds to pow(2, 30) */
+      pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 4.0)
+        {
+          pOut[i] = 0x7FFFFFFF;
+        }
+    }
+}
+
+
+/**
+ * @brief  Converts float to fixed q28 format
+ * @param  uint32_t     number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t * pOut,
+                       uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+    /* 268435456.0f corresponds to pow(2, 28) */
+      pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 8.0)
+        {
+          pOut[i] = 0x7FFFFFFF;
+        }
+    }
+}
+
+/**
+ * @brief  Clip the float values to +/- 1
+ * @param  pIn      input buffer
+ * @param  numSamples   number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+      if (pIn[i] > 1.0f)
+      {
+        pIn[i] = 1.0;
+      }
+      else if ( pIn[i] < -1.0f)
+      {
+        pIn[i] = -1.0;
+      }
+
+    }
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_ADD_TEST(suffix)          \
+    MATRIX_DEFINE_TEST_TEMPLATE_ELT2(           \
+        mat_add,                                \
+        suffix,                                 \
+        MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT,     \
+        MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS,  \
+        MATRIX_COMPARE_INTERFACE)
+
+JTEST_ARM_MAT_ADD_TEST(f32);
+JTEST_ARM_MAT_ADD_TEST(q31);
+JTEST_ARM_MAT_ADD_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_add_tests)
+{
+    JTEST_TEST_CALL(arm_mat_add_f32_test);
+    JTEST_TEST_CALL(arm_mat_add_q31_test);
+    JTEST_TEST_CALL(arm_mat_add_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_CMPLX_MULT_TEST(suffix, comparison_interface) \
+    MATRIX_DEFINE_TEST_TEMPLATE_ELT2(                               \
+        mat_cmplx_mult,                                             \
+        suffix,                                                     \
+        MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,                   \
+        MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,                \
+        comparison_interface)
+
+JTEST_ARM_MAT_CMPLX_MULT_TEST(f32, MATRIX_SNR_COMPARE_INTERFACE);
+JTEST_ARM_MAT_CMPLX_MULT_TEST(q31, MATRIX_COMPARE_INTERFACE);
+
+/*--------------------------------------------------------------------------------*/
+/* Q15 Uses a Different interface than the others. */
+/*--------------------------------------------------------------------------------*/
+
+#define ARM_mat_cmplx_mult_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+    PAREN(input_a_ptr, input_b_ptr,                                     \
+          (void *) &matrix_output_fut,                                  \
+          (q15_t *) matrix_output_scratch)
+
+JTEST_DEFINE_TEST(arm_mat_cmplx_mult_q15_test, arm_mat_cmplx_mult_q15)
+{
+    MATRIX_TEST_TEMPLATE_ELT2(
+        matrix_q15_a_inputs,
+        matrix_q15_b_inputs,
+        arm_matrix_instance_q15 * ,
+        arm_matrix_instance_q15,
+        TYPE_FROM_ABBREV(q15),
+        arm_mat_cmplx_mult_q15,
+        ARM_mat_cmplx_mult_q15_INPUT_INTERFACE,
+        ref_mat_cmplx_mult_q15,
+        REF_mat_cmplx_mult_INPUT_INTERFACE,
+        MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,
+        MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,
+        MATRIX_COMPARE_INTERFACE);
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_cmplx_mult_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mat_cmplx_mult_f32_test);
+    JTEST_TEST_CALL(arm_mat_cmplx_mult_q31_test);
+    JTEST_TEST_CALL(arm_mat_cmplx_mult_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_INIT_TEST(suffix)                     \
+    JTEST_DEFINE_TEST(arm_mat_init_##suffix##_test,         \
+                      arm_mat_init_##suffix)                \
+    {                                                       \
+        const uint16_t rows = 4;                            \
+        const uint16_t cols = 2;                            \
+        arm_matrix_instance_##suffix  matrix = {0};         \
+        /*  TYPE_FROM_ABBREV(suffix) data[rows*cols] = {0}; */ \
+            TYPE_FROM_ABBREV(suffix) data[4*2] = {0}; \
+                                                            \
+            arm_mat_init_##suffix(&matrix,                  \
+                                  rows,                     \
+                                  cols,                     \
+                                  data);                    \
+                                                            \
+                JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n", \
+                     (int)matrix.numRows,                   \
+                     (int)matrix.numCols);                  \
+                                                            \
+                if ((matrix.numRows == rows) &&             \
+                    (matrix.numCols == cols) &&             \
+                    (matrix.pData == data))                 \
+                {                                           \
+                    return JTEST_TEST_PASSED;               \
+                }                                           \
+                else                                        \
+                {                                           \
+                    return JTEST_TEST_FAILED;               \
+                }                                           \
+                                                            \
+    }
+
+JTEST_ARM_MAT_INIT_TEST(f32);
+JTEST_ARM_MAT_INIT_TEST(q31);
+JTEST_ARM_MAT_INIT_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_init_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mat_init_f32_test);
+    JTEST_TEST_CALL(arm_mat_init_q31_test);
+    JTEST_TEST_CALL(arm_mat_init_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+JTEST_DEFINE_TEST(arm_mat_inverse_f32_test, arm_mat_inverse_f32)
+{
+    TEMPLATE_DO_ARR_DESC(
+        mat_idx, arm_matrix_instance_f32 *, mat_ptr, matrix_f32_invertible_inputs
+        ,
+        JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n",                
+                 (int)mat_ptr->numRows,                         
+                 (int)mat_ptr->numCols); 
+      
+        if (MATRIX_TEST_VALID_SQUARE_DIMENSIONS(arm_matrix_instance_f32 *, mat_ptr))
+        {
+            MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f32 *, mat_ptr);
+
+            /* arm_mat_inverse_f32() modifies its source input. Use the scratch
+             * buffer to store a copy of the intended input. */
+            {
+                float32_t * original_pdata_ptr = mat_ptr->pData;
+
+                memcpy(matrix_output_scratch,
+                       mat_ptr->pData,
+                       mat_ptr->numRows * mat_ptr->numCols * sizeof(float32_t));
+                mat_ptr->pData = (void*) &matrix_output_scratch;
+
+                JTEST_COUNT_CYCLES(arm_mat_inverse_f32(mat_ptr, &matrix_output_fut));
+                mat_ptr->pData = original_pdata_ptr;
+            }
+
+            ref_mat_inverse_f32(mat_ptr, &matrix_output_ref);
+
+            MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_f32,
+                                         float32_t);
+        });
+
+    return JTEST_TEST_PASSED;
+}
+
+JTEST_DEFINE_TEST(arm_mat_inverse_f64_test, arm_mat_inverse_f64)
+{
+    TEMPLATE_DO_ARR_DESC(
+        mat_idx, arm_matrix_instance_f64 *, mat_ptr, matrix_f64_invertible_inputs
+        ,
+        JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n",                
+                         (int)mat_ptr->numRows,                         
+                         (int)mat_ptr->numCols);    
+                         
+        if (MATRIX_TEST_VALID_SQUARE_DIMENSIONS(arm_matrix_instance_f64 *, mat_ptr))
+        {
+            MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f64 *, mat_ptr);
+
+            /* arm_mat_inverse_f64() modifies its source input. Use the scratch
+             * buffer to store a copy of the intended input. */
+            {
+                float64_t * original_pdata_ptr = mat_ptr->pData;
+
+                memcpy(matrix_output_scratch,
+                       mat_ptr->pData,
+                       mat_ptr->numRows * mat_ptr->numCols * sizeof(float64_t));
+                mat_ptr->pData = (void*) &matrix_output_scratch;
+
+                JTEST_COUNT_CYCLES(arm_mat_inverse_f64(mat_ptr, &matrix_output_fut64));
+                mat_ptr->pData = original_pdata_ptr;
+            }
+
+            ref_mat_inverse_f64(mat_ptr, &matrix_output_ref64);
+
+            MATRIX_DBL_SNR_COMPARE_INTERFACE(arm_matrix_instance_f64);
+        });
+
+    return JTEST_TEST_PASSED;
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_inverse_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mat_inverse_f32_test);
+    JTEST_TEST_CALL(arm_mat_inverse_f64_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_MULT_FAST_TEST(suffix)            \
+    MATRIX_DEFINE_TEST_TEMPLATE_ELT2(                   \
+        mat_mult_fast,                                  \
+        suffix,                                         \
+        MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,       \
+        MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,    \
+        MATRIX_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_MAT_MULT_FAST_TEST(q31);
+
+/*--------------------------------------------------------------------------------*/
+/* Q15 Uses a Different interface than the others. */
+/*--------------------------------------------------------------------------------*/
+
+#define ARM_mat_mult_fast_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+    PAREN(input_a_ptr, input_b_ptr,                                     \
+          (void *) &matrix_output_fut,                                  \
+          (q15_t *) matrix_output_scratch)
+
+JTEST_DEFINE_TEST(arm_mat_mult_fast_q15_test, arm_mat_mult_fast_q15)
+{
+    MATRIX_TEST_TEMPLATE_ELT2(
+        matrix_q15_a_inputs,
+        matrix_q15_b_inputs,
+        arm_matrix_instance_q15 * ,
+        arm_matrix_instance_q15,
+        TYPE_FROM_ABBREV(q15),
+        arm_mat_mult_fast_q15,
+        ARM_mat_mult_fast_q15_INPUT_INTERFACE,
+        ref_mat_mult_fast_q15,
+        REF_mat_mult_fast_INPUT_INTERFACE,
+        MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,
+        MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,
+        MATRIX_SNR_COMPARE_INTERFACE);
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_mult_fast_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mat_mult_fast_q31_test);
+    JTEST_TEST_CALL(arm_mat_mult_fast_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_MULT_TEST(suffix)                 \
+    MATRIX_DEFINE_TEST_TEMPLATE_ELT2(                   \
+        mat_mult,                                       \
+        suffix,                                         \
+        MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,       \
+        MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,    \
+        MATRIX_COMPARE_INTERFACE)
+
+JTEST_ARM_MAT_MULT_TEST(f32);
+JTEST_ARM_MAT_MULT_TEST(q31);
+
+/*--------------------------------------------------------------------------------*/
+/* Q15 Uses a Different interface than the others. */
+/*--------------------------------------------------------------------------------*/
+
+#define ARM_mat_mult_q15_INPUT_INTERFACE(input_a_ptr, input_b_ptr) \
+    PAREN(input_a_ptr, input_b_ptr,                                     \
+          (void *) &matrix_output_fut,                                  \
+          (q15_t *) matrix_output_scratch)
+
+JTEST_DEFINE_TEST(arm_mat_mult_q15_test, arm_mat_mult_q15)
+{
+    MATRIX_TEST_TEMPLATE_ELT2(
+        matrix_q15_a_inputs,
+        matrix_q15_b_inputs,
+        arm_matrix_instance_q15 * ,
+        arm_matrix_instance_q15,
+        TYPE_FROM_ABBREV(q15),
+        arm_mat_mult_q15,
+        ARM_mat_mult_q15_INPUT_INTERFACE,
+        ref_mat_mult_q15,
+        REF_mat_mult_INPUT_INTERFACE,
+        MATRIX_TEST_CONFIG_MULTIPLICATIVE_OUTPUT,
+        MATRIX_TEST_VALID_MULTIPLICATIVE_DIMENSIONS,
+        MATRIX_COMPARE_INTERFACE);
+}
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_mult_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mat_mult_f32_test);
+    JTEST_TEST_CALL(arm_mat_mult_q31_test);
+    JTEST_TEST_CALL(arm_mat_mult_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+/* This is for the two fixed point cases */
+#define JTEST_ARM_MAT_SCALE_TEST(suffix,type)                           \
+    JTEST_DEFINE_TEST(arm_mat_scale_##suffix##_test, arm_mat_scale_##suffix) \
+    {                                                                   \
+        uint32_t i,j;                                                   \
+                                                                        \
+        TEMPLATE_DO_ARR_DESC(                                           \
+            mat_idx, arm_matrix_instance_##suffix *,                    \
+            mat_ptr, matrix_##suffix##_b_inputs                         \
+            ,                                                           \
+            MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(                         \
+                arm_matrix_instance_##suffix *, mat_ptr);               \
+                                                                        \
+            for(i=0;i<MATRIX_MAX_COEFFS_LEN;i++)                        \
+            {                                                           \
+                for(j=0;j<MATRIX_MAX_SHIFTS_LEN;j++)                    \
+                {                                                       \
+                    JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n",       \
+                         (int)mat_ptr->numRows,                         \
+                         (int)mat_ptr->numCols);                        \
+                                                                        \
+                    JTEST_COUNT_CYCLES(                                 \
+                        arm_mat_scale_##suffix(mat_ptr,                 \
+                                               matrix_##suffix##_scale_values[i], \
+                                               matrix_shift_values[j],  \
+                                               (arm_matrix_instance_##suffix*) &matrix_output_fut)); \
+                                                                        \
+                    ref_mat_scale_##suffix(mat_ptr,                     \
+                                           matrix_##suffix##_scale_values[i], \
+                                           matrix_shift_values[j],      \
+                                           (arm_matrix_instance_##suffix*) &matrix_output_ref); \
+                                                                        \
+                        MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_##suffix, \
+                                                     type);             \
+                }                                                       \
+            });                                                         \
+                                                                        \
+        return JTEST_TEST_PASSED;                                       \
+    }
+
+JTEST_DEFINE_TEST(arm_mat_scale_f32_test, arm_mat_scale_f32)
+{
+    uint32_t i;
+
+    TEMPLATE_DO_ARR_DESC(
+        mat_idx, arm_matrix_instance_f32 *, mat_ptr, matrix_f32_b_inputs
+        ,
+        MATRIX_TEST_CONFIG_SAMESIZE_OUTPUT(arm_matrix_instance_f32 *, mat_ptr);
+
+        for(i=0;i<MATRIX_MAX_COEFFS_LEN;i++)
+        {
+            JTEST_DUMP_STRF("Matrix Dimensions: %dx%d\n",                
+                         (int)mat_ptr->numRows,                         
+                         (int)mat_ptr->numCols);                        
+            JTEST_COUNT_CYCLES(arm_mat_scale_f32(mat_ptr, matrix_f32_scale_values[i], &matrix_output_fut));
+
+            ref_mat_scale_f32(mat_ptr, matrix_f32_scale_values[i], &matrix_output_ref);
+
+            MATRIX_SNR_COMPARE_INTERFACE(arm_matrix_instance_f32,
+                                         float32_t);
+        });
+
+    return JTEST_TEST_PASSED;
+}
+
+JTEST_ARM_MAT_SCALE_TEST(q31,q31_t);
+JTEST_ARM_MAT_SCALE_TEST(q15,q15_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_scale_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mat_scale_f32_test);
+    JTEST_TEST_CALL(arm_mat_scale_q31_test);
+    JTEST_TEST_CALL(arm_mat_scale_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_SUB_TEST(suffix)          \
+    MATRIX_DEFINE_TEST_TEMPLATE_ELT2(           \
+        mat_sub,                                \
+        suffix,                                 \
+        MATRIX_TEST_CONFIG_ADDITIVE_OUTPUT,     \
+        MATRIX_TEST_VALID_ADDITIVE_DIMENSIONS,  \
+        MATRIX_COMPARE_INTERFACE)
+
+JTEST_ARM_MAT_SUB_TEST(f32);
+JTEST_ARM_MAT_SUB_TEST(q31);
+JTEST_ARM_MAT_SUB_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_sub_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mat_sub_f32_test);
+    JTEST_TEST_CALL(arm_mat_sub_q31_test);
+    JTEST_TEST_CALL(arm_mat_sub_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c

+#include "jtest.h"
+#include "matrix_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "matrix_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAT_TRANS_TEST(suffix)        \
+    MATRIX_DEFINE_TEST_TEMPLATE_ELT1(           \
+        mat_trans,                              \
+        suffix,                                 \
+        MATRIX_TEST_CONFIG_TRANSPOSE_OUTPUT,    \
+        MATRIX_TEST_VALID_DIMENSIONS_ALWAYS)
+
+JTEST_ARM_MAT_TRANS_TEST(f32);
+JTEST_ARM_MAT_TRANS_TEST(q31);
+JTEST_ARM_MAT_TRANS_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mat_trans_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mat_trans_f32_test);
+    JTEST_TEST_CALL(arm_mat_trans_q31_test);
+    JTEST_TEST_CALL(arm_mat_trans_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c

+#include "arm_math.h"
+#include "matrix_test_data.h"
+#include "type_abbrev.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_fut_data[2*MATRIX_TEST_MAX_ELTS] = {0};
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_ref_data[2*MATRIX_TEST_MAX_ELTS] = {0};
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_scratch[MATRIX_TEST_MAX_ELTS] = {0};
+
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_fut[MATRIX_TEST_MAX_ELTS];
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_output_f32_ref[MATRIX_TEST_MAX_ELTS];
+
+arm_matrix_instance_f32 matrix_output_fut = {
+    0,
+    0,
+    (float32_t *) &matrix_output_fut_data
+};
+
+arm_matrix_instance_f32 matrix_output_ref = {
+    0,
+    0,
+    (float32_t *) &matrix_output_ref_data
+};
+
+arm_matrix_instance_f64 matrix_output_fut64 = {
+    0,
+    0,
+    (float64_t *) &matrix_output_fut_data
+};
+
+arm_matrix_instance_f64 matrix_output_ref64 = {
+    0,
+    0,
+    (float64_t *) &matrix_output_ref_data
+};
+
+/*--------------------------------------------------------------------------------*/
+/* Data Buckets */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Pool of random data to base matrix inputs from.
+ */
+float32_t matrix_f32_100_rand[100] = {
+    -45.0345569674258,  -11.0261163038747, -14.6841428777929,
+    0.0345569674258,    -11.0261163038747, -14.6841428777929,
+    -20.3679194392227,  27.5712678608402,  -12.1390617339732,
+    -19.8753669720509,  42.3379642103244,  -23.7788252219155,
+    -23.7517765301667,  40.2716109915281,  -25.8308714086167,
+    32.1194040197959,   24.4692807074156,  -1.32083675968276,
+    31.1580458282477,   -2.90766514824093, -6.97926086704160,
+    10.2843089382083,   30.1014622769739,  44.4787189721646,
+    -9.60878544118853,  -48.4596562348445, -31.1044984967456,
+    -6.41414114190809,  3.28255887994549,  -26.9511839788442,
+    -31.5183679875864,  21.1215780433683,  -47.0779722437854,
+    -0.913590753192006, -40.3545474831611, -45.6976198342192,
+    18.6775433365315,   -5.32162505701938, -14.9272896423117,
+    34.4308792695389,   40.4880968679893,  -27.8253265982760,
+    42.8854139478045,   -1.07473615999811, -36.8026707393665,
+    -33.1009970537296,  -31.6488844262730, -19.3650527983443,
+    43.9001561999887,   -30.5235710432951, 47.9748378356085,
+    -38.2582349144194,  23.0330862855453,  -16.2280590178623,
+    44.2050590775485,   14.9115474956452,  -13.1515403509664,
+    0.850865538112700,  37.5942811492984,  -27.4078219027601,
+    -6.11300268738968,  -20.3324126781673, -1.13910261964209,
+    40.0053846417662,   45.6134540229802,  23.1722385658670,
+    12.5618560729690,   1.07715641721097,  5.01563428984222,
+    -32.9291952852141,  -38.8880776559401, -18.1221698074118,
+    7.85250610234389,   -13.0753218879785, 7.52085950784656,
+    14.7745963136307,   28.0227435151377,  31.7627708322262,
+    12.2475086001227,   -27.2335702183447, -24.1935304087933,
+    -7.58332402861928,  -26.2716420228479, -38.8797244706213,
+    -44.0220457052844,  -4.90762935690551, -41.8874231134215,
+    29.4831416883453,   8.70447045314168,  -6.43013158961009,
+    -9.12801538874479,  0.785828466111815, -4.11511718200689,
+    28.0252068321138,   -26.5220086627594, 4.70088922863450,
+    42.9385970968730,   14.4318130193692,  -29.2257707266972,
+    46.3088539286913
+};
+
+float64_t matrix_f64_100_rand[100] = {
+    -45.0345569674258,  -11.0261163038747, -14.6841428777929,
+    0.0345569674258,    -11.0261163038747, -14.6841428777929,
+    -20.3679194392227,  27.5712678608402,  -12.1390617339732,
+    -19.8753669720509,  42.3379642103244,  -23.7788252219155,
+    -23.7517765301667,  40.2716109915281,  -25.8308714086167,
+    32.1194040197959,   24.4692807074156,  -1.32083675968276,
+    31.1580458282477,   -2.90766514824093, -6.97926086704160,
+    10.2843089382083,   30.1014622769739,  44.4787189721646,
+    -9.60878544118853,  -48.4596562348445, -31.1044984967456,
+    -6.41414114190809,  3.28255887994549,  -26.9511839788442,
+    -31.5183679875864,  21.1215780433683,  -47.0779722437854,
+    -0.913590753192006, -40.3545474831611, -45.6976198342192,
+    18.6775433365315,   -5.32162505701938, -14.9272896423117,
+    34.4308792695389,   40.4880968679893,  -27.8253265982760,
+    42.8854139478045,   -1.07473615999811, -36.8026707393665,
+    -33.1009970537296,  -31.6488844262730, -19.3650527983443,
+    43.9001561999887,   -30.5235710432951, 47.9748378356085,
+    -38.2582349144194,  23.0330862855453,  -16.2280590178623,
+    44.2050590775485,   14.9115474956452,  -13.1515403509664,
+    0.850865538112700,  37.5942811492984,  -27.4078219027601,
+    -6.11300268738968,  -20.3324126781673, -1.13910261964209,
+    40.0053846417662,   45.6134540229802,  23.1722385658670,
+    12.5618560729690,   1.07715641721097,  5.01563428984222,
+    -32.9291952852141,  -38.8880776559401, -18.1221698074118,
+    7.85250610234389,   -13.0753218879785, 7.52085950784656,
+    14.7745963136307,   28.0227435151377,  31.7627708322262,
+    12.2475086001227,   -27.2335702183447, -24.1935304087933,
+    -7.58332402861928,  -26.2716420228479, -38.8797244706213,
+    -44.0220457052844,  -4.90762935690551, -41.8874231134215,
+    29.4831416883453,   8.70447045314168,  -6.43013158961009,
+    -9.12801538874479,  0.785828466111815, -4.11511718200689,
+    28.0252068321138,   -26.5220086627594, 4.70088922863450,
+    42.9385970968730,   14.4318130193692,  -29.2257707266972,
+    46.3088539286913
+};
+
+MATRIX_TEST_BIGGEST_INPUT_TYPE matrix_zeros[MATRIX_TEST_MAX_ELTS] = {0};
+
+const float32_t matrix_f32_scale_values[MATRIX_MAX_COEFFS_LEN] =
+{
+        43.0264275639  , -17.0525215570 , -94.8488973910 , -8.1924989580  ,
+        7.2830326091   , 66.8368719314  , 33.9778190671  , 117.8652289772 ,
+        -129.6077797465, -14.6420815368 , 18.0239223278  , 1.0000000000   ,
+        55.0375037651  , 1.8674609862   , 0.00000000000  , -33.5750364909
+};
+
+const q31_t matrix_q31_scale_values[MATRIX_MAX_COEFFS_LEN] =
+{
+    0x0201DC90, 0x211F0D7C, 0x80000000, 0xF573B824,
+    0xE85ED05B, 0x311DFB52, 0x3529E750, 0x00000000,
+    0x7FFFFFFF, 0x21FA525A, 0x0971FD45, 0x05547B68,
+    0x270C6366, 0x06FDD5A6, 0xF7025315, 0xB1155A1E
+};
+
+const q15_t matrix_q15_scale_values[MATRIX_MAX_COEFFS_LEN] =
+{
+    0x0201, 0x211F, 0x8000, 0xF573,
+    0xE85E, 0x311D, 0x3529, 0x0000,
+    0x7FFF, 0x21FA, 0x0971, 0x0554,
+    0x270C, 0x06FD, 0xF702, 0xB115
+};
+
+const int32_t matrix_shift_values[MATRIX_MAX_SHIFTS_LEN] =
+{
+    -16, -7, 0, 7, 16
+};
+
+/*--------------------------------------------------------------------------------*/
+/* Matrix Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Define matrices by suffix (f32, q31, q15) for use in test cases.
+ *
+ *  The rand1 and rand2 suffixes get their data from the same pool of random
+ *  data, but their starting points differ by 1 element.
+ *
+ *  Makes available:
+ *  - matrix_`suffix`_1x1_rand1/2
+ *  - matrix_`suffix`_1x4_rand1/2
+ *  - matrix_`suffix`_2x4_rand1/2
+ *  - matrix_`suffix`_4x4_rand1/2
+ */
+#define MATRIX_DEFINE_MATRICES(suffix)                              \
+    arm_matrix_instance_##suffix matrix_##suffix##_1x1_rand1 =      \
+        {1, 1, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand };  \
+    arm_matrix_instance_##suffix matrix_##suffix##_1x1_rand2 =      \
+        {1, 1, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \
+    arm_matrix_instance_##suffix matrix_##suffix##_1x1_zeros =      \
+        {1, 1, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros};          \
+                                                                    \
+    arm_matrix_instance_##suffix matrix_##suffix##_1x4_rand1 =      \
+        {1, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand };  \
+    arm_matrix_instance_##suffix matrix_##suffix##_1x4_rand2 =      \
+        {1, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \
+    arm_matrix_instance_##suffix matrix_##suffix##_1x4_zeros =      \
+        {1, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros};          \
+                                                                    \
+    arm_matrix_instance_##suffix matrix_##suffix##_2x4_rand1 =      \
+        {2, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand };  \
+    arm_matrix_instance_##suffix matrix_##suffix##_2x4_rand2 =      \
+        {2, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \
+    arm_matrix_instance_##suffix matrix_##suffix##_2x4_zeros =      \
+        {2, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros};          \
+                                                                    \
+    arm_matrix_instance_##suffix matrix_##suffix##_4x4_rand1 =      \
+        {4, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_f32_100_rand };  \
+    arm_matrix_instance_##suffix matrix_##suffix##_4x4_rand2 =      \
+        {4, 4, (TYPE_FROM_ABBREV(suffix) *) (matrix_f32_100_rand+1)}; \
+    arm_matrix_instance_##suffix matrix_##suffix##_4x4_zeros =      \
+        {4, 4, (TYPE_FROM_ABBREV(suffix) *) matrix_zeros}
+
+MATRIX_DEFINE_MATRICES(f64);
+MATRIX_DEFINE_MATRICES(f32);
+MATRIX_DEFINE_MATRICES(q31);
+MATRIX_DEFINE_MATRICES(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Matrix-Input Arrays */
+/*--------------------------------------------------------------------------------*/
+
+/* Define Input #ARR_DESC_t by suffix.
+ *
+ * Taking inputs in parallel from the 'a' and 'b' arrays yields the following
+ * test cases:
+ * - 1x1 multiplication by zero
+ * - 1x1 multiplication between random numbers
+ * - 1x1 * 1x4 valid dimension interaction
+ * - 1x1 * 2x4 invalid dimension interaction
+ * - 2x4 * 4x4 larger valid dimension interaction
+ * - 4x4 * 4x4 larger valid dimension interaction
+ */
+#define MATRIX_DEFINE_INPUTS(suffix)                        \
+    ARR_DESC_DEFINE(arm_matrix_instance_##suffix *,         \
+                    matrix_##suffix##_a_inputs,             \
+                    6,                                      \
+                    CURLY(                                  \
+                        &matrix_##suffix##_1x1_rand1,       \
+                        &matrix_##suffix##_1x1_rand1,       \
+                        &matrix_##suffix##_1x1_rand1,       \
+                        &matrix_##suffix##_1x1_rand1,       \
+                        &matrix_##suffix##_2x4_rand1,       \
+                        &matrix_##suffix##_4x4_rand1        \
+                        ));                                 \
+                                                            \
+    ARR_DESC_DEFINE(arm_matrix_instance_##suffix *,         \
+                    matrix_##suffix##_b_inputs,             \
+                    6,                                      \
+                    CURLY(                                  \
+                        &matrix_##suffix##_1x1_zeros,       \
+                        &matrix_##suffix##_1x1_rand2,       \
+                        &matrix_##suffix##_1x4_rand2,       \
+                        &matrix_##suffix##_2x4_rand2,       \
+                        &matrix_##suffix##_4x4_rand2,       \
+                        &matrix_##suffix##_4x4_rand2        \
+                        ));                                 \
+                                                            \
+    ARR_DESC_DEFINE(arm_matrix_instance_##suffix *,         \
+                    matrix_##suffix##_invertible_inputs,    \
+                    4,                                      \
+                    CURLY(                                  \
+                        &matrix_##suffix##_1x1_rand1,       \
+                        &matrix_##suffix##_1x1_rand2,       \
+                        &matrix_##suffix##_4x4_rand1,       \
+                        &matrix_##suffix##_4x4_rand2        \
+                        ))                                  \
+
+MATRIX_DEFINE_INPUTS(f64);
+MATRIX_DEFINE_INPUTS(f32);
+MATRIX_DEFINE_INPUTS(q31);
+MATRIX_DEFINE_INPUTS(q15);

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c

+#include "jtest.h"
+#include "matrix_tests.h"
+
+JTEST_DEFINE_GROUP(matrix_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_GROUP_CALL(mat_add_tests);
+    JTEST_GROUP_CALL(mat_cmplx_mult_tests);
+    JTEST_GROUP_CALL(mat_init_tests);
+    JTEST_GROUP_CALL(mat_inverse_tests);
+    JTEST_GROUP_CALL(mat_mult_tests);
+    JTEST_GROUP_CALL(mat_mult_fast_tests);
+    JTEST_GROUP_CALL(mat_sub_tests);
+    JTEST_GROUP_CALL(mat_trans_tests);
+    JTEST_GROUP_CALL(mat_scale_tests);
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c

+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MAX_TEST(suffix)              \
+    STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(   \
+        max,                                    \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        STATISTICS_COMPARE_INTERFACE)
+
+JTEST_ARM_MAX_TEST(f32);
+JTEST_ARM_MAX_TEST(q31);
+JTEST_ARM_MAX_TEST(q15);
+JTEST_ARM_MAX_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(max_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_max_f32_test);
+    JTEST_TEST_CALL(arm_max_q31_test);
+    JTEST_TEST_CALL(arm_max_q15_test);
+    JTEST_TEST_CALL(arm_max_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c

+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MEAN_TEST(suffix)             \
+    STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(   \
+        mean,                                   \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        STATISTICS_COMPARE_INTERFACE)
+
+JTEST_ARM_MEAN_TEST(f32);
+JTEST_ARM_MEAN_TEST(q31);
+JTEST_ARM_MEAN_TEST(q15);
+JTEST_ARM_MEAN_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(mean_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_mean_f32_test);
+    JTEST_TEST_CALL(arm_mean_q31_test);
+    JTEST_TEST_CALL(arm_mean_q15_test);
+    JTEST_TEST_CALL(arm_mean_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c

+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_MIN_TEST(suffix)              \
+    STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(   \
+        min,                                    \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        STATISTICS_COMPARE_INTERFACE)
+
+JTEST_ARM_MIN_TEST(f32);
+JTEST_ARM_MIN_TEST(q31);
+JTEST_ARM_MIN_TEST(q15);
+JTEST_ARM_MIN_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(min_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_min_f32_test);
+    JTEST_TEST_CALL(arm_min_q31_test);
+    JTEST_TEST_CALL(arm_min_q15_test);
+    JTEST_TEST_CALL(arm_min_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c

+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_POWER_TEST(suffix, output_type)   \
+    STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(       \
+        power,                                      \
+        suffix,                                     \
+        TYPE_FROM_ABBREV(suffix),                   \
+        TYPE_FROM_ABBREV(suffix),                   \
+        STATISTICS_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_POWER_TEST(f32, float32_t);
+JTEST_ARM_POWER_TEST(q31, q63_t);
+JTEST_ARM_POWER_TEST(q15, q63_t);
+JTEST_ARM_POWER_TEST(q7,  q31_t);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(power_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_power_f32_test);
+    JTEST_TEST_CALL(arm_power_q31_test);
+    JTEST_TEST_CALL(arm_power_q15_test);
+    JTEST_TEST_CALL(arm_power_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c

+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_RMS_TEST(suffix)              \
+    STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(   \
+        rms,                                    \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        STATISTICS_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_RMS_TEST(f32);
+JTEST_ARM_RMS_TEST(q31);
+JTEST_ARM_RMS_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(rms_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_rms_f32_test);
+    JTEST_TEST_CALL(arm_rms_q31_test);
+    JTEST_TEST_CALL(arm_rms_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c

+#include "statistics_test_data.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+
+ARR_DESC_DEFINE(STATISTICS_BIGGEST_INPUT_TYPE,
+                statistics_output_fut,
+                STATISTICS_MAX_INPUT_ELEMENTS,
+                CURLY(0));
+
+ARR_DESC_DEFINE(STATISTICS_BIGGEST_INPUT_TYPE,
+                statistics_output_ref,
+                STATISTICS_MAX_INPUT_ELEMENTS,
+                CURLY(0));
+
+uint32_t statistics_idx_fut = 0;
+uint32_t statistics_idx_ref = 0;
+
+STATISTICS_BIGGEST_INPUT_TYPE
+statistics_output_f32_ref[STATISTICS_MAX_INPUT_ELEMENTS];
+
+STATISTICS_BIGGEST_INPUT_TYPE
+statistics_output_f32_fut[STATISTICS_MAX_INPUT_ELEMENTS];
+
+/*--------------------------------------------------------------------------------*/
+/* Block Sizes */
+/*--------------------------------------------------------------------------------*/
+
+/* 
+  To change test parameter values add/remove values inside CURLY and update 
+  the preceeding parameter to reflect the number of values inside CURLY. 
+*/
+
+ARR_DESC_DEFINE(uint32_t,
+                statistics_block_sizes,
+                4,
+                CURLY(1, 2, 15, 32));
+
+/*--------------------------------------------------------------------------------*/
+/* Test Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+                statistics_f_32,
+                32,
+                CURLY(
+                    -0.0865129623056441 , -0.3331168756476194,
+                    0.0250664612949661  , 0.0575352840717098,
+                    -0.2292942701362928 , 0.2381830931285998,
+                    0.2378328403304206  ,  -0.0075266553186635,
+                    0.0654584722817308  , 0.0349278285641849,
+                    -0.0373417155362879 , 0.1451581096586606,
+                    -0.1176633086028378 , 0.4366371636394202,
+                    -0.0272791766173191 , 0.0227862627041619,
+                    0.2133536422718378  ,  0.0118562921047211,
+                    -0.0191296810967338 , -0.1664698927300045,
+                    0.0588821632785281  , -0.2672363715875608,
+                    0.1428649103637904  ,  0.3247124128892542,
+                    -0.1383551403404573 , 0.1715993345656525,
+                    0.2508002843205065  , -0.3187459152894954,
+                    -0.2881928863802040 , 0.1142295247316356,
+                    -0.0799771155430726 , 0.1379994750928690
+                    ));
+
+
+ARR_DESC_DEFINE_SUBSET(statistics_f_31,
+                       statistics_f_32,
+                       31);
+
+ARR_DESC_DEFINE_SUBSET(statistics_f_15,
+                       statistics_f_32,
+                       15);
+
+ARR_DESC_DEFINE_SUBSET(statistics_f_2,
+                       statistics_f_32,
+                       2);
+
+ARR_DESC_DEFINE(float32_t,
+                statistics_zeros,
+                32,
+                CURLY(0));
+
+/* Aggregate all float datasets */
+ARR_DESC_DEFINE(ARR_DESC_t *,
+                statistics_f_all,
+                4,
+                CURLY(
+                    &statistics_zeros,
+                    &statistics_f_2,
+                    &statistics_f_15,
+                    &statistics_f_32
+                    ));

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c

+#include "jtest.h"
+#include "statistics_tests.h"
+
+JTEST_DEFINE_GROUP(statistics_tests)
+{
+    JTEST_GROUP_CALL(max_tests);
+    JTEST_GROUP_CALL(mean_tests);
+    JTEST_GROUP_CALL(min_tests);
+    JTEST_GROUP_CALL(power_tests);
+    JTEST_GROUP_CALL(rms_tests);
+    JTEST_GROUP_CALL(std_tests);
+    JTEST_GROUP_CALL(var_tests);
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c

+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_STD_TEST(suffix)              \
+    STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(   \
+        std,                                    \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        STATISTICS_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_STD_TEST(f32);
+JTEST_ARM_STD_TEST(q31);
+JTEST_ARM_STD_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(std_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_std_f32_test);
+    JTEST_TEST_CALL(arm_std_q31_test);
+    JTEST_TEST_CALL(arm_std_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c

+#include "jtest.h"
+#include "statistics_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "statistics_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_VAR_TEST(suffix)              \
+    STATISTICS_DEFINE_TEST_TEMPLATE_BUF1_BLK(   \
+        var,                                    \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        STATISTICS_SNR_COMPARE_INTERFACE)
+
+JTEST_ARM_VAR_TEST(f32);
+JTEST_ARM_VAR_TEST(q31);
+JTEST_ARM_VAR_TEST(q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(var_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_var_f32_test);
+    JTEST_TEST_CALL(arm_var_q31_test);
+    JTEST_TEST_CALL(arm_var_q15_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c

+#include "jtest.h"
+#include "support_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "support_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_COPY_TEST(suffix)             \
+    SUPPORT_DEFINE_TEST_TEMPLATE_BUF1_BLK(      \
+        copy,                                   \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        SUPPORT_COMPARE_INTERFACE)
+
+JTEST_ARM_COPY_TEST(f32);
+JTEST_ARM_COPY_TEST(q31);
+JTEST_ARM_COPY_TEST(q15);
+JTEST_ARM_COPY_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(copy_tests)
+{
+    JTEST_TEST_CALL(arm_copy_f32_test);
+    JTEST_TEST_CALL(arm_copy_q31_test);
+    JTEST_TEST_CALL(arm_copy_q15_test);
+    JTEST_TEST_CALL(arm_copy_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c

+#include "jtest.h"
+#include "support_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "support_templates.h"
+#include "type_abbrev.h"
+
+#define JTEST_ARM_FILL_TEST(suffix)             \
+    SUPPORT_DEFINE_TEST_TEMPLATE_ELT1_BLK(      \
+        fill,                                   \
+        suffix,                                 \
+        TYPE_FROM_ABBREV(suffix),               \
+        TYPE_FROM_ABBREV(suffix),               \
+        SUPPORT_COMPARE_INTERFACE)
+
+JTEST_ARM_FILL_TEST(f32);
+JTEST_ARM_FILL_TEST(q31);
+JTEST_ARM_FILL_TEST(q15);
+JTEST_ARM_FILL_TEST(q7);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(fill_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_fill_f32_test);
+    JTEST_TEST_CALL(arm_fill_q31_test);
+    JTEST_TEST_CALL(arm_fill_q15_test);
+    JTEST_TEST_CALL(arm_fill_q7_test);
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c

+#include "arm_math.h"
+#include "support_test_data.h"
+
+#define MAX_INPUT_ELEMENTS 32
+#define BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Input/Output Buffers */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(BIGGEST_INPUT_TYPE,
+                support_output_fut,
+                MAX_INPUT_ELEMENTS,
+                CURLY(0));
+
+ARR_DESC_DEFINE(BIGGEST_INPUT_TYPE,
+                support_output_ref,
+                MAX_INPUT_ELEMENTS,
+                CURLY(0));
+
+/*--------------------------------------------------------------------------------*/
+/* Block Sizes */
+/*--------------------------------------------------------------------------------*/
+
+/* 
+  To change test parameter values add/remove values inside CURLY and update 
+  the preceeding parameter to reflect the number of values inside CURLY. 
+*/
+
+ARR_DESC_DEFINE(uint32_t,
+                support_block_sizes,
+                4,
+                CURLY( 2, 7, 15, 32));
+
+/*--------------------------------------------------------------------------------*/
+/* Numbers */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(uint32_t,
+                support_elts,
+                4,
+                CURLY( 0, 1, 0x80000000, 0x7fffffff));
+
+/*--------------------------------------------------------------------------------*/
+/* Test Data */
+/*--------------------------------------------------------------------------------*/
+
+ARR_DESC_DEFINE(float32_t,
+                support_f_32,
+                32,
+                CURLY(
+                      0.24865986 , -0.13364227, -0.27233250 , -7.33488200,
+                      0.42190653 , 1.17435880 , -0.49824914 , 0.87883663,
+                      0.63066370 , 1.80275680 , -84.83916000, -2.06773800,
+                      7.63452500 , 1.01487610 , -0.65785825 , 1.78019030,
+                      -0.34160388, 0.68546050 , -1.81721590 , -0.10340453,
+                      -4.48600340, -1.69763480, -1.26022340 , -1.58457480,
+                      0.51993870 , 2.83526470 , -0.21502694 , -0.57690346,
+                      -0.22945681, 0.79509383 , 0.07275216  , -2.16279080
+                      ));
+
+/* Alias the 32 element array with wrappers that end sooner. */
+ARR_DESC_DEFINE_SUBSET(support_f_15,
+                       support_f_32,
+                       15);
+
+ARR_DESC_DEFINE_SUBSET(support_f_2,
+                       support_f_32,
+                       2);
+
+ARR_DESC_DEFINE(float32_t,
+                support_zeros,
+                32,
+                CURLY(0));
+
+/* Aggregate all float datasets. */
+ARR_DESC_DEFINE(ARR_DESC_t *,
+                support_f_all,
+                4,
+                CURLY(
+                      &support_zeros,
+                      &support_f_2,
+                      &support_f_15,
+                      &support_f_32
+                      ));

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c

+#include "jtest.h"
+#include "support_tests.h"
+
+JTEST_DEFINE_GROUP(support_tests)
+{
+    JTEST_GROUP_CALL(copy_tests);
+    JTEST_GROUP_CALL(fill_tests);
+    JTEST_GROUP_CALL(x_to_y_tests);
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c

+#include "jtest.h"
+#include "support_test_data.h"
+#include "arr_desc.h"
+#include "arm_math.h"           /* FUTs */
+#include "ref.h"                /* Reference Functions */
+#include "test_templates.h"
+#include "support_templates.h"
+#include "type_abbrev.h"
+
+/* Aliases to play nicely with templates. */
+#define arm_f32_to_q31 arm_float_to_q31
+#define arm_f32_to_q15 arm_float_to_q15
+#define arm_f32_to_q7  arm_float_to_q7
+#define arm_q31_to_f32 arm_q31_to_float
+#define arm_q15_to_f32 arm_q15_to_float
+#define arm_q7_to_f32  arm_q7_to_float
+#define ref_f32_to_q31 ref_float_to_q31
+#define ref_f32_to_q15 ref_float_to_q15
+#define ref_f32_to_q7  ref_float_to_q7
+#define ref_q31_to_f32 ref_q31_to_float
+#define ref_q15_to_f32 ref_q15_to_float
+#define ref_q7_to_f32  ref_q7_to_float
+
+#define JTEST_ARM_X_TO_Y_TEST(prefix, suffix)               \
+    JTEST_DEFINE_TEST(arm_##prefix##_to_##suffix##_test,    \
+                      arm_##prefix##_to_##suffix)           \
+    {                                                       \
+        TEST_TEMPLATE_BUF1_BLK(                             \
+            support_f_all,                                  \
+            support_block_sizes,                            \
+            TYPE_FROM_ABBREV(prefix),                       \
+            TYPE_FROM_ABBREV(suffix),                       \
+            arm_##prefix##_to_##suffix,                     \
+            ARM_x_to_y_INPUT_INTERFACE,                     \
+            ref_##prefix##_to_##suffix,                     \
+            REF_x_to_y_INPUT_INTERFACE,                     \
+            SUPPORT_COMPARE_INTERFACE);                     \
+    }
+
+JTEST_ARM_X_TO_Y_TEST(f32, q31);
+JTEST_ARM_X_TO_Y_TEST(f32, q15);
+JTEST_ARM_X_TO_Y_TEST(f32, q7);
+
+JTEST_ARM_X_TO_Y_TEST(q31, f32);
+JTEST_ARM_X_TO_Y_TEST(q31, q15);
+JTEST_ARM_X_TO_Y_TEST(q31, q7);
+
+JTEST_ARM_X_TO_Y_TEST(q15, f32);
+JTEST_ARM_X_TO_Y_TEST(q15, q31);
+JTEST_ARM_X_TO_Y_TEST(q15, q7);
+
+JTEST_ARM_X_TO_Y_TEST(q7, f32);
+JTEST_ARM_X_TO_Y_TEST(q7, q31);
+JTEST_ARM_X_TO_Y_TEST(q7, q15);
+
+/*--------------------------------------------------------------------------------*/
+/* Collect all tests in a group. */
+/*--------------------------------------------------------------------------------*/
+
+JTEST_DEFINE_GROUP(x_to_y_tests)
+{
+    /*
+      To skip a test, comment it out.
+    */
+    JTEST_TEST_CALL(arm_f32_to_q31_test);
+    JTEST_TEST_CALL(arm_f32_to_q15_test);
+    JTEST_TEST_CALL(arm_f32_to_q7_test);
+
+    JTEST_TEST_CALL(arm_q31_to_f32_test);
+    JTEST_TEST_CALL(arm_q31_to_q15_test);
+    JTEST_TEST_CALL(arm_q31_to_q7_test);
+
+    JTEST_TEST_CALL(arm_q15_to_f32_test);
+    JTEST_TEST_CALL(arm_q15_to_q31_test);
+    JTEST_TEST_CALL(arm_q15_to_q7_test);
+
+    JTEST_TEST_CALL(arm_q7_to_f32_test);
+    JTEST_TEST_CALL(arm_q7_to_q31_test);
+    JTEST_TEST_CALL(arm_q7_to_q15_test);
+}